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Configuring SystemVerilog RTL Models
Mike Thompson edited this page 2026-05-13 10:55:00 -04:00

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10 Commits

Author SHA1 Message Date
Mike Thompson
f857db1972 ...and one more... 2026-05-13 10:55:00 -04:00
Mike Thompson
391e570a1d Missed a few... 2026-05-13 10:50:52 -04:00
Mike Thompson
31457e29e7 A better way to highlight keywords with a preceding tick 2026-05-13 10:45:27 -04:00
Mike Thompson
868802932e Expanded description of CVA6 cfg generation 2026-05-12 13:06:45 -04:00
Mike Thompson
a4758f037e Use better macro expansion example 2026-05-12 10:08:28 -04:00
Mike Thompson
151fd80f81 Add "macro expansion" sub-section 2026-05-11 16:18:50 -04:00
Mike Thompson
de8cf46234 Cleanup 2026-05-11 16:07:00 -04:00
Mike Thompson
66919ecfbd Update based on feedback from @cainria. 2026-05-11 15:56:49 -04:00
Mike Thompson
5a12fec03d (1) Add license header, (2) Use SystemVerilog fenced code blocks. 2026-05-11 12:02:11 -04:00
Mike Thompson
aacaf4d7b5 Created Configuring SystemVerilog RTL Models (markdown) 2026-04-27 12:38:52 -04:00