add fetch_enable_i (#118)

* add fetch_enable_i

* fix missign signals

* removed unused signals

rtl/cve2_controller.sv

@@ -16,6 +16,7 @@ module cve2_controller #(
   input  logic                  clk_i,
   input  logic                  rst_ni,
 
+  input  logic                  fetch_enable_i,          // core can fetch instructions leave RESET state
   output logic                  ctrl_busy_o,             // core is busy processing instrs
 
   // decoder related signals
@@ -368,9 +369,11 @@ module cve2_controller #(
         instr_req_o   = 1'b0;
         pc_mux_o      = PC_BOOT;
         pc_set_o      = 1'b1;
-        ctrl_fsm_ns   = BOOT_SET;
+        if (fetch_enable_i == 1'b1)
+        begin
+          ctrl_fsm_ns = BOOT_SET;
+        end
       end
-
       BOOT_SET: begin
         // copy boot address to instr fetch address
         instr_req_o   = 1'b1;

rtl/cve2_core.sv

@@ -103,6 +103,7 @@ module cve2_core import cve2_pkg::*; #(
 `endif
 
   // CPU Control Signals
+  input  logic                         fetch_enable_i,
   output logic                         core_busy_o
 );
 
@@ -262,7 +263,6 @@ module cve2_core import cve2_pkg::*; #(
 
   logic        perf_instr_ret_wb;
   logic        perf_instr_ret_compressed_wb;
-  logic        perf_instr_ret_compressed_wb_spec;
   logic        perf_iside_wait;
   logic        perf_dside_wait;
   logic        perf_wfi_wait;
@@ -368,6 +368,7 @@ module cve2_core import cve2_pkg::*; #(
     .rst_ni(rst_ni),
 
     // Processor Enable
+    .fetch_enable_i(fetch_enable_i),
     .ctrl_busy_o   (ctrl_busy),
     .illegal_insn_o(illegal_insn_id),
 

rtl/cve2_cs_registers.sv

@@ -215,7 +215,7 @@ module cve2_cs_registers #(
   logic        unused_mhpmcounterh_we_1;
   logic        unused_mhpmcounter_incr_1;
 
-  logic [63:0] minstret_next, minstret_raw;
+  logic [63:0] minstret_raw;
 
   // Debug / trigger registers
   logic [31:0] tselect_rdata;
@@ -1220,7 +1220,7 @@ module cve2_cs_registers #(
     .counter_we_i(mhpmcounter_we[2]),
     .counter_val_i(csr_wdata_int),
     .counter_val_o(minstret_raw),
-    .counter_val_upd_o(minstret_next)
+    .counter_val_upd_o()
   );
 
   // Where the writeback stage is present instruction in ID observing value of minstret must take

rtl/cve2_ex_block.sv

@@ -137,6 +137,7 @@ module cve2_ex_block #(
       .imd_val_q_i       (imd_val_q_i),
       .imd_val_d_o       (multdiv_imd_val_d),
       .imd_val_we_o      (multdiv_imd_val_we),
+      .multdiv_ready_id_i(1'b1),
       .multdiv_result_o  (multdiv_result)
     );
   end else if (RV32M == RV32MFast || RV32M == RV32MSingleCycle) begin : gen_multdiv_fast

rtl/cve2_id_stage.sv

@@ -26,6 +26,7 @@ module cve2_id_stage #(
   input  logic                      clk_i,
   input  logic                      rst_ni,
 
+  input  logic                      fetch_enable_i,
   output logic                      ctrl_busy_o,
   output logic                      illegal_insn_o,
 
@@ -454,6 +455,7 @@ module cve2_id_stage #(
     .clk_i (clk_i),
     .rst_ni(rst_ni),
 
+    .fetch_enable_i(fetch_enable_i),
     .ctrl_busy_o(ctrl_busy_o),
 
     // decoder related signals
@@ -492,7 +494,7 @@ module cve2_id_stage #(
     .lsu_addr_last_i(lsu_addr_last_i),
     .load_err_i     (lsu_load_err_i),
     .store_err_i    (lsu_store_err_i),
-
+    .id_exception_o (),
     // jump/branch control
     .branch_set_i     (branch_set),
     .branch_not_set_i (branch_not_set),

rtl/cve2_top.sv

@@ -95,6 +95,7 @@ module cve2_top import cve2_pkg::*; #(
 `endif
 
   // CPU Control Signals
+  input  logic                         fetch_enable_i,
   output logic                         core_sleep_o
 );
 
@@ -117,6 +118,7 @@ module cve2_top import cve2_pkg::*; #(
   logic                        clk;
   logic                        core_busy_d, core_busy_q;
   logic                        clock_en;
+  logic                        fetch_enable_d, fetch_enable_q;
   logic                        irq_pending;
 
   /////////////////////
@@ -126,13 +128,16 @@ module cve2_top import cve2_pkg::*; #(
   always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       core_busy_q <= 1'b0;
+      fetch_enable_q <= 1'b0;
     end else begin
       core_busy_q <= core_busy_d;
+      fetch_enable_q <= fetch_enable_d;
     end
   end
 
   assign clock_en     = core_busy_q | debug_req_i | irq_pending | irq_nm_i;
   assign core_sleep_o = ~clock_en;
+  assign fetch_enable_d = fetch_enable_i ? 1'b1 : fetch_enable_q;
 
   cve2_clock_gate core_clock_gate_i (
     .clk_i    (clk_i),
@@ -224,7 +229,8 @@ module cve2_top import cve2_pkg::*; #(
     .rvfi_ext_mcycle,
 `endif
 
-    .core_busy_o   (core_busy_d)
+    .fetch_enable_i (fetch_enable_q),
+    .core_busy_o    (core_busy_d)
   );
 
   ////////////////////////

rtl/cve2_wb.sv

@@ -65,7 +65,5 @@ module cve2_wb #(
                          ({32{rf_wdata_wb_mux_we[1]}} & rf_wdata_wb_mux[1]);
   assign rf_we_wb_o    = |rf_wdata_wb_mux_we;
 
-  `DV_FCOV_SIGNAL_GEN_IF(logic, wb_valid, g_writeback_stage.wb_valid_q, 1'b0)
-
   `ASSERT(RFWriteFromOneSourceOnly, $onehot0(rf_wdata_wb_mux_we))
 endmodule