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Bugfix: Generate Erroneous Illegal Insn
This commit fixes three possible cases for erroneous generation of
illegal instruction signals. Also, the bit-slices considered for
decoding ALU instructions are corrected to better reflect their
encoding specifications.
* Fix decoding of orc_b in illegal_insn generation.
* Insn[31] is no longer checked for generation of illegal instructions:
This bit is part of the rs3 register adress for ternary
bitmanipulation instructions (zbt).
* Correct bit-slicing for ALU reg-immediate instructions according
to specification: immediates are encoded in the range
insn[26:20] in all cases. Where a shift-amount is encoded, bits
[26:25] will have no effect, but will no longer generate
illegal instructions.
Signed-off-by: ganoam <gnoam@live.com>
This commit is contained in:
ganoam
Pirmin Vogel
parent
5a188342e7
commit
06f50ddeac
2 changed files with 207 additions and 207 deletions
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@ -335,14 +335,14 @@ module ibex_decoder #(
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3'b111: illegal_insn = 1'b0;
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3'b001: begin
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unique case (instr[31:25])
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7'b000_0000: illegal_insn = 1'b0; // slli
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7'b001_0000: illegal_insn = RV32B ? 1'b0 : 1'b1; // sloi
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7'b011_0000: begin
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unique case(instr[24:20])
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5'b00000, // clz
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5'b00001, // ctz
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5'b00010: illegal_insn = RV32B ? 1'b0 : 1'b1; // pcnt
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unique case (instr[31:27])
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5'b0_0000: illegal_insn = 1'b0; // slli
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5'b0_0100: illegal_insn = RV32B ? 1'b0 : 1'b1; // sloi
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5'b0_1100: begin
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unique case(instr[26:20])
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7'b00_00000, // clz
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7'b00_00001, // ctz
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7'b00_00010: illegal_insn = RV32B ? 1'b0 : 1'b1; // pcnt
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default: illegal_insn = 1'b1;
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endcase
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end
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@ -352,24 +352,29 @@ module ibex_decoder #(
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3'b101: begin
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if (instr[26]) begin
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illegal_insn = RV32B ? 1'b0 : 1'b1; // fsri
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illegal_insn = RV32B ? 1'b0 : 1'b1; // fsri
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end else begin
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unique case (instr[31:25])
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7'b000_0000, // srli
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7'b010_0000: illegal_insn = 1'b0; // srai
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unique case (instr[31:27])
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5'b0_0000, // srli
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5'b0_1000: illegal_insn = 1'b0; // srai
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7'b001_0000, // sroi
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7'b011_0000: illegal_insn = RV32B ? 1'b0 : 1'b1; // rori
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5'b0_0100, // sroi
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5'b0_1100: illegal_insn = RV32B ? 1'b0 : 1'b1; // rori
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7'b011_0100: begin
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5'b0_1101: begin
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unique case(instr[24:20])
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5'b11111, // rev
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5'b11000, // rev8
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5'b00111: illegal_insn = RV32B ? 1'b0 : 1'b1; // orc.b
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default: illegal_insn = 1'b1;
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5'b1_1111, // rev
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5'b1_1000: illegal_insn = RV32B ? 1'b0 : 1'b1; // rev8
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default: illegal_insn = 1'b1;
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endcase
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end
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5'b0_0101: begin
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if(instr[24:20] == 5'b0_0111) begin
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illegal_insn = RV32B ? 1'b0 : 1'b1; // orc.b
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end else begin
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illegal_insn = 1'b1;
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end
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end
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default: illegal_insn = 1'b1;
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endcase
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end
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@ -383,95 +388,91 @@ module ibex_decoder #(
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rf_ren_a_o = 1'b1;
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rf_ren_b_o = 1'b1;
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rf_we = 1'b1;
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if (instr[31]) begin
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illegal_insn = 1'b1;
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if ({instr[26], instr[13:12]} == {1'b1, 2'b01}) begin
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illegal_insn = RV32B ? 1'b0 : 1'b1; // cmix / cmov / fsl / fsr
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end else begin
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if ({instr[26], instr[13:12]} == {1'b1, 2'b01}) begin
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illegal_insn = RV32B ? 1'b0 : 1'b1; // cmix / cmov / fsl / fsr
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end else begin
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unique case ({instr[30:25], instr[14:12]})
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// RV32I ALU operations
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{6'b00_0000, 3'b000},
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{6'b10_0000, 3'b000},
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{6'b00_0000, 3'b010},
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{6'b00_0000, 3'b011},
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{6'b00_0000, 3'b100},
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{6'b00_0000, 3'b110},
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{6'b00_0000, 3'b111},
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{6'b00_0000, 3'b001},
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{6'b00_0000, 3'b101},
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{6'b10_0000, 3'b101}: illegal_insn = 1'b0;
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unique case ({instr[31:25], instr[14:12]})
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// RV32I ALU operations
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{7'b000_0000, 3'b000},
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{7'b010_0000, 3'b000},
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{7'b000_0000, 3'b010},
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{7'b000_0000, 3'b011},
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{7'b000_0000, 3'b100},
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{7'b000_0000, 3'b110},
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{7'b000_0000, 3'b111},
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{7'b000_0000, 3'b001},
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{7'b000_0000, 3'b101},
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{7'b010_0000, 3'b101}: illegal_insn = 1'b0;
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// supported RV32B instructions (zbb)
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{6'b10_0000, 3'b111}, // andn
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{6'b10_0000, 3'b110}, // orn
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{6'b10_0000, 3'b100}, // xnor
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{6'b01_0000, 3'b001}, // slo
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{6'b01_0000, 3'b101}, // sro
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{6'b11_0000, 3'b001}, // rol
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{6'b11_0000, 3'b101}, // ror
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{6'b00_0101, 3'b100}, // min
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{6'b00_0101, 3'b101}, // max
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{6'b00_0101, 3'b110}, // minu
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{6'b00_0101, 3'b111}, // maxu
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{6'b00_0100, 3'b100}, // pack
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{6'b10_0100, 3'b100}, // packu
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{6'b00_0100, 3'b111}: illegal_insn = RV32B ? 1'b0 : 1'b1; // packh
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// supported RV32B instructions (zbb)
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{7'b010_0000, 3'b111}, // andn
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{7'b010_0000, 3'b110}, // orn
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{7'b010_0000, 3'b100}, // xnor
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{7'b001_0000, 3'b001}, // slo
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{7'b001_0000, 3'b101}, // sro
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{7'b011_0000, 3'b001}, // rol
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{7'b011_0000, 3'b101}, // ror
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{7'b000_0101, 3'b100}, // min
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{7'b000_0101, 3'b101}, // max
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{7'b000_0101, 3'b110}, // minu
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{7'b000_0101, 3'b111}, // maxu
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{7'b000_0100, 3'b100}, // pack
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{7'b010_0100, 3'b100}, // packu
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{7'b000_0100, 3'b111}: illegal_insn = RV32B ? 1'b0 : 1'b1; // packh
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// supported RV32M instructions
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{6'b00_0001, 3'b000}: begin // mul
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multdiv_operator_o = MD_OP_MULL;
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mult_en_o = RV32M ? 1'b1 : 1'b0;
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multdiv_signed_mode_o = 2'b00;
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illegal_insn = RV32M ? 1'b0 : 1'b1;
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end
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{6'b00_0001, 3'b001}: begin // mulh
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multdiv_operator_o = MD_OP_MULH;
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mult_en_o = RV32M ? 1'b1 : 1'b0;
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multdiv_signed_mode_o = 2'b11;
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illegal_insn = RV32M ? 1'b0 : 1'b1;
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end
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{6'b00_0001, 3'b010}: begin // mulhsu
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multdiv_operator_o = MD_OP_MULH;
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mult_en_o = RV32M ? 1'b1 : 1'b0;
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multdiv_signed_mode_o = 2'b01;
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illegal_insn = RV32M ? 1'b0 : 1'b1;
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end
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{6'b00_0001, 3'b011}: begin // mulhu
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multdiv_operator_o = MD_OP_MULH;
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mult_en_o = RV32M ? 1'b1 : 1'b0;
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multdiv_signed_mode_o = 2'b00;
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illegal_insn = RV32M ? 1'b0 : 1'b1;
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end
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{6'b00_0001, 3'b100}: begin // div
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multdiv_operator_o = MD_OP_DIV;
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div_en_o = RV32M ? 1'b1 : 1'b0;
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multdiv_signed_mode_o = 2'b11;
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illegal_insn = RV32M ? 1'b0 : 1'b1;
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end
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{6'b00_0001, 3'b101}: begin // divu
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multdiv_operator_o = MD_OP_DIV;
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div_en_o = RV32M ? 1'b1 : 1'b0;
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multdiv_signed_mode_o = 2'b00;
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illegal_insn = RV32M ? 1'b0 : 1'b1;
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end
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{6'b00_0001, 3'b110}: begin // rem
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multdiv_operator_o = MD_OP_REM;
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div_en_o = RV32M ? 1'b1 : 1'b0;
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multdiv_signed_mode_o = 2'b11;
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illegal_insn = RV32M ? 1'b0 : 1'b1;
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end
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{6'b00_0001, 3'b111}: begin // remu
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multdiv_operator_o = MD_OP_REM;
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div_en_o = RV32M ? 1'b1 : 1'b0;
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multdiv_signed_mode_o = 2'b00;
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illegal_insn = RV32M ? 1'b0 : 1'b1;
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end
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default: begin
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illegal_insn = 1'b1;
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end
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endcase
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end
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// supported RV32M instructions
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{7'b000_0001, 3'b000}: begin // mul
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multdiv_operator_o = MD_OP_MULL;
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mult_en_o = RV32M ? 1'b1 : 1'b0;
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multdiv_signed_mode_o = 2'b00;
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illegal_insn = RV32M ? 1'b0 : 1'b1;
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end
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{7'b000_0001, 3'b001}: begin // mulh
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multdiv_operator_o = MD_OP_MULH;
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mult_en_o = RV32M ? 1'b1 : 1'b0;
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multdiv_signed_mode_o = 2'b11;
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illegal_insn = RV32M ? 1'b0 : 1'b1;
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end
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{7'b000_0001, 3'b010}: begin // mulhsu
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multdiv_operator_o = MD_OP_MULH;
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mult_en_o = RV32M ? 1'b1 : 1'b0;
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multdiv_signed_mode_o = 2'b01;
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illegal_insn = RV32M ? 1'b0 : 1'b1;
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end
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{7'b000_0001, 3'b011}: begin // mulhu
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multdiv_operator_o = MD_OP_MULH;
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mult_en_o = RV32M ? 1'b1 : 1'b0;
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multdiv_signed_mode_o = 2'b00;
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illegal_insn = RV32M ? 1'b0 : 1'b1;
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end
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{7'b000_0001, 3'b100}: begin // div
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multdiv_operator_o = MD_OP_DIV;
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div_en_o = RV32M ? 1'b1 : 1'b0;
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multdiv_signed_mode_o = 2'b11;
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illegal_insn = RV32M ? 1'b0 : 1'b1;
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end
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{7'b000_0001, 3'b101}: begin // divu
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multdiv_operator_o = MD_OP_DIV;
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div_en_o = RV32M ? 1'b1 : 1'b0;
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multdiv_signed_mode_o = 2'b00;
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illegal_insn = RV32M ? 1'b0 : 1'b1;
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end
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{7'b000_0001, 3'b110}: begin // rem
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multdiv_operator_o = MD_OP_REM;
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div_en_o = RV32M ? 1'b1 : 1'b0;
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multdiv_signed_mode_o = 2'b11;
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illegal_insn = RV32M ? 1'b0 : 1'b1;
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end
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{7'b000_0001, 3'b111}: begin // remu
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multdiv_operator_o = MD_OP_REM;
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div_en_o = RV32M ? 1'b1 : 1'b0;
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multdiv_signed_mode_o = 2'b00;
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illegal_insn = RV32M ? 1'b0 : 1'b1;
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end
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default: begin
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illegal_insn = 1'b1;
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end
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endcase
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end
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end
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@ -750,17 +751,14 @@ module ibex_decoder #(
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3'b001: begin
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if (RV32B) begin
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// We don't factor in instr[31] here to make the ALU decoder more symmetric for
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// Reg-Reg and Reg-Imm ALU operations. Instr[31] is only needed to detect illegal
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// encodings for Reg-Reg ALU operations (see non-ALU decoder).
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unique case (instr[30:25])
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6'b00_0000: alu_operator_o = ALU_SLL; // Shift Left Logical by Immediate
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6'b01_0000: alu_operator_o = ALU_SLO; // Shift Left Ones by Immediate
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6'b11_0000: begin
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unique case (instr[24:20])
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5'b00000: alu_operator_o = ALU_CLZ; // Count Leading Zeros
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5'b00001: alu_operator_o = ALU_CTZ; // Count Trailing Zeros
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5'b00010: alu_operator_o = ALU_PCNT; // Count Set Bits
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unique case (instr[31:27])
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5'b0_0000: alu_operator_o = ALU_SLL; // Shift Left Logical by Immediate
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5'b0_0100: alu_operator_o = ALU_SLO; // Shift Left Ones by Immediate
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5'b0_1100: begin
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unique case (instr[26:20])
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7'b000_0000: alu_operator_o = ALU_CLZ; // Count Leading Zeros
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7'b000_0001: alu_operator_o = ALU_CTZ; // Count Trailing Zeros
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7'b000_0010: alu_operator_o = ALU_PCNT; // Count Set Bits
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default: ;
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endcase
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end
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@ -782,37 +780,35 @@ module ibex_decoder #(
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end else begin
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use_rs3 = 1'b1;
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end
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end else begin
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unique case (instr_alu[31:27])
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5'b0_0000: alu_operator_o = ALU_SRL; // Shift Right Logical by Immediate
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5'b0_1000: alu_operator_o = ALU_SRA; // Shift Right Arithmetically by Immediate
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5'b0_0100: alu_operator_o = ALU_SRO; // Shift Right Ones by Immediate
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5'b0_1100: begin
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alu_operator_o = ALU_ROR; // Rotate Right by Immediate
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alu_multicycle_o = 1'b1;
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end
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5'b0_1101: begin
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if (instr_alu[24:20] == 5'b1_1111) begin
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alu_operator_o = ALU_REV; // Reverse
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end else if (instr_alu[24:20] == 5'b11000) begin
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alu_operator_o = ALU_REV8; // Byte-swap
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end
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end
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5'b0_0101: begin
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if (instr_alu[24:20] == 5'b0_0111) begin
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alu_operator_o = ALU_ORCB; // Byte-wise Reverse and Or-Combine
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end
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end
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default: ;
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endcase
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end
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// We don't factor in instr[31] here to make the ALU decoder more symmetric for
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// Reg-Reg and Reg-Imm ALU operations. Instr[31] is only needed to detect illegal
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// encodings for Reg-Reg ALU operations (see non-ALU decoder).
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unique case (instr_alu[30:25])
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6'b00_0000: alu_operator_o = ALU_SRL; // Shift Right Logical by Immediate
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6'b10_0000: alu_operator_o = ALU_SRA; // Shift Right Arithmetically by Immediate
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6'b01_0000: alu_operator_o = ALU_SRO; // Shift Right Ones by Immediate
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6'b11_0000: begin
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alu_operator_o = ALU_ROR; // Rotate Right by Immediate
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alu_multicycle_o = 1'b1;
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end
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6'b11_0100: begin
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if (instr_alu[24:20] == 5'b11111) begin
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alu_operator_o = ALU_REV; // Reverse
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end else if (instr_alu[24:20] == 5'b11000) begin
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alu_operator_o = ALU_REV8; // Byte-swap
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end
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end
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6'b01_0100: begin
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if (instr_alu[24:20] == 5'b00111) begin
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alu_operator_o = ALU_ORCB; // Byte-wise Reverse and Or-Combine
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end
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end
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default: ;
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endcase
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end else begin
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if (instr_alu[31:25] == 7'b0) begin
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if (instr_alu[31:27] == 5'b0_0000) begin
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alu_operator_o = ALU_SRL; // Shift Right Logical by Immediate
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end else if (instr_alu[31:25] == 7'b010_0000) begin
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end else if (instr_alu[31:27] == 5'b0_1000) begin
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alu_operator_o = ALU_SRA; // Shift Right Arithmetically by Immediate
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end
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end
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@ -868,64 +864,65 @@ module ibex_decoder #(
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default: ;
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endcase
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end
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end else begin
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unique case ({instr_alu[31:25], instr_alu[14:12]})
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// RV32I ALU operations
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{7'b000_0000, 3'b000}: alu_operator_o = ALU_ADD; // Add
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{7'b010_0000, 3'b000}: alu_operator_o = ALU_SUB; // Sub
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{7'b000_0000, 3'b010}: alu_operator_o = ALU_SLT; // Set Lower Than
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{7'b000_0000, 3'b011}: alu_operator_o = ALU_SLTU; // Set Lower Than Unsigned
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{7'b000_0000, 3'b100}: alu_operator_o = ALU_XOR; // Xor
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{7'b000_0000, 3'b110}: alu_operator_o = ALU_OR; // Or
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{7'b000_0000, 3'b111}: alu_operator_o = ALU_AND; // And
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{7'b000_0000, 3'b001}: alu_operator_o = ALU_SLL; // Shift Left Logical
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{7'b000_0000, 3'b101}: alu_operator_o = ALU_SRL; // Shift Right Logical
|
||||
{7'b010_0000, 3'b101}: alu_operator_o = ALU_SRA; // Shift Right Arithmetic
|
||||
|
||||
// RV32B ALU Operations
|
||||
{7'b001_0000, 3'b001}: if (RV32B) alu_operator_o = ALU_SLO; // Shift Left Ones
|
||||
{7'b001_0000, 3'b101}: if (RV32B) alu_operator_o = ALU_SRO; // Shift Right Ones
|
||||
{7'b011_0000, 3'b001}: begin
|
||||
if (RV32B) begin
|
||||
alu_operator_o = ALU_ROL; // Rotate Left
|
||||
alu_multicycle_o = 1'b1;
|
||||
end
|
||||
end
|
||||
{7'b011_0000, 3'b101}: begin
|
||||
if (RV32B) begin
|
||||
alu_operator_o = ALU_ROR; // Rotate Right
|
||||
alu_multicycle_o = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
{7'b000_0101, 3'b100}: if (RV32B) alu_operator_o = ALU_MIN; // Minimum
|
||||
{7'b000_0101, 3'b101}: if (RV32B) alu_operator_o = ALU_MAX; // Maximum
|
||||
{7'b000_0101, 3'b110}: if (RV32B) alu_operator_o = ALU_MINU; // Minimum Unsigned
|
||||
{7'b000_0101, 3'b111}: if (RV32B) alu_operator_o = ALU_MAXU; // Maximum Unsigned
|
||||
|
||||
{7'b000_0100, 3'b100}: if (RV32B) alu_operator_o = ALU_PACK; // Pack Lower Halves
|
||||
{7'b010_0100, 3'b100}: if (RV32B) alu_operator_o = ALU_PACKU; // Pack Upper Halves
|
||||
{7'b000_0100, 3'b111}: if (RV32B) alu_operator_o = ALU_PACKH; // Pack LSB Bytes
|
||||
|
||||
{7'b010_0000, 3'b100}: if (RV32B) alu_operator_o = ALU_XNOR; // Xnor
|
||||
{7'b010_0000, 3'b110}: if (RV32B) alu_operator_o = ALU_ORN; // Orn
|
||||
{7'b010_0000, 3'b111}: if (RV32B) alu_operator_o = ALU_ANDN; // Andn
|
||||
|
||||
// supported RV32M instructions, all use the same ALU operation
|
||||
{7'b000_0001, 3'b000}, // mul
|
||||
{7'b000_0001, 3'b001}, // mulh
|
||||
{7'b000_0001, 3'b010}, // mulhsu
|
||||
{7'b000_0001, 3'b011}, // mulhu
|
||||
{7'b000_0001, 3'b100}, // div
|
||||
{7'b000_0001, 3'b101}, // divu
|
||||
{7'b000_0001, 3'b110}, // rem
|
||||
{7'b000_0001, 3'b111}: begin // remu
|
||||
multdiv_sel_o = 1'b1;
|
||||
alu_operator_o = ALU_ADD;
|
||||
end
|
||||
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
unique case ({instr_alu[30:25], instr_alu[14:12]})
|
||||
// RV32I ALU operations
|
||||
{6'b00_0000, 3'b000}: alu_operator_o = ALU_ADD; // Add
|
||||
{6'b10_0000, 3'b000}: alu_operator_o = ALU_SUB; // Sub
|
||||
{6'b00_0000, 3'b010}: alu_operator_o = ALU_SLT; // Set Lower Than
|
||||
{6'b00_0000, 3'b011}: alu_operator_o = ALU_SLTU; // Set Lower Than Unsigned
|
||||
{6'b00_0000, 3'b100}: alu_operator_o = ALU_XOR; // Xor
|
||||
{6'b00_0000, 3'b110}: alu_operator_o = ALU_OR; // Or
|
||||
{6'b00_0000, 3'b111}: alu_operator_o = ALU_AND; // And
|
||||
{6'b00_0000, 3'b001}: alu_operator_o = ALU_SLL; // Shift Left Logical
|
||||
{6'b00_0000, 3'b101}: alu_operator_o = ALU_SRL; // Shift Right Logical
|
||||
{6'b10_0000, 3'b101}: alu_operator_o = ALU_SRA; // Shift Right Arithmetic
|
||||
|
||||
// RV32B ALU Operations
|
||||
{6'b01_0000, 3'b001}: if (RV32B) alu_operator_o = ALU_SLO; // Shift Left Ones
|
||||
{6'b01_0000, 3'b101}: if (RV32B) alu_operator_o = ALU_SRO; // Shift Right Ones
|
||||
{6'b11_0000, 3'b001}: begin
|
||||
if (RV32B) begin
|
||||
alu_operator_o = ALU_ROL; // Rotate Left
|
||||
alu_multicycle_o = 1'b1;
|
||||
end
|
||||
end
|
||||
{6'b11_0000, 3'b101}: begin
|
||||
if (RV32B) begin
|
||||
alu_operator_o = ALU_ROR; // Rotate Right
|
||||
alu_multicycle_o = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
{6'b00_0101, 3'b100}: if (RV32B) alu_operator_o = ALU_MIN; // Minimum
|
||||
{6'b00_0101, 3'b101}: if (RV32B) alu_operator_o = ALU_MAX; // Maximum
|
||||
{6'b00_0101, 3'b110}: if (RV32B) alu_operator_o = ALU_MINU; // Minimum Unsigned
|
||||
{6'b00_0101, 3'b111}: if (RV32B) alu_operator_o = ALU_MAXU; // Maximum Unsigned
|
||||
|
||||
{6'b00_0100, 3'b100}: if (RV32B) alu_operator_o = ALU_PACK; // Pack Lower Halves
|
||||
{6'b10_0100, 3'b100}: if (RV32B) alu_operator_o = ALU_PACKU; // Pack Upper Halves
|
||||
{6'b00_0100, 3'b111}: if (RV32B) alu_operator_o = ALU_PACKH; // Pack LSB Bytes
|
||||
|
||||
{6'b10_0000, 3'b100}: if (RV32B) alu_operator_o = ALU_XNOR; // Xnor
|
||||
{6'b10_0000, 3'b110}: if (RV32B) alu_operator_o = ALU_ORN; // Orn
|
||||
{6'b10_0000, 3'b111}: if (RV32B) alu_operator_o = ALU_ANDN; // Andn
|
||||
|
||||
// supported RV32M instructions, all use the same ALU operation
|
||||
{6'b00_0001, 3'b000}, // mul
|
||||
{6'b00_0001, 3'b001}, // mulh
|
||||
{6'b00_0001, 3'b010}, // mulhsu
|
||||
{6'b00_0001, 3'b011}, // mulhu
|
||||
{6'b00_0001, 3'b100}, // div
|
||||
{6'b00_0001, 3'b101}, // divu
|
||||
{6'b00_0001, 3'b110}, // rem
|
||||
{6'b00_0001, 3'b111}: begin // remu
|
||||
multdiv_sel_o = 1'b1;
|
||||
alu_operator_o = ALU_ADD;
|
||||
end
|
||||
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
|
||||
/////////////
|
||||
|
|
|
|||
|
|
@ -74,15 +74,18 @@ parameter logic [31:0] INSN_PMULHU = { 7'b0000001, 10'b?, 3'b011, 5'b?, {OPCODE
|
|||
// RV32B
|
||||
// OPIMM
|
||||
// ZBB
|
||||
parameter logic [31:0] INSN_SLOI = { 7'b00100 , 10'b?, 3'b001, 5'b?, {OPCODE_OP_IMM} };
|
||||
parameter logic [31:0] INSN_SROI = { 7'b0010000 , 10'b?, 3'b101, 5'b?, {OPCODE_OP_IMM} };
|
||||
parameter logic [31:0] INSN_RORI = { 7'b0110000 , 10'b?, 3'b101, 5'b?, {OPCODE_OP_IMM} };
|
||||
parameter logic [31:0] INSN_SLOI = { 5'b00100 , 12'b?, 3'b001, 5'b?, {OPCODE_OP_IMM} };
|
||||
parameter logic [31:0] INSN_SROI = { 5'b00100 , 12'b?, 3'b101, 5'b?, {OPCODE_OP_IMM} };
|
||||
parameter logic [31:0] INSN_RORI = { 5'b01100 , 12'b?, 3'b101, 5'b?, {OPCODE_OP_IMM} };
|
||||
parameter logic [31:0] INSN_CLZ = { 12'b011000000000, 5'b? , 3'b001, 5'b?, {OPCODE_OP_IMM} };
|
||||
parameter logic [31:0] INSN_CTZ = { 12'b011000000001, 5'b? , 3'b001, 5'b?, {OPCODE_OP_IMM} };
|
||||
parameter logic [31:0] INSN_PCNT = { 12'b011000000010, 5'b? , 3'b001, 5'b?, {OPCODE_OP_IMM} };
|
||||
parameter logic [31:0] INSN_REV = { 12'b011010011111, 5'b? , 3'b101, 5'b?, {OPCODE_OP_IMM} };
|
||||
parameter logic [31:0] INSN_REV8 = { 12'b011010011000, 5'b? , 3'b101, 5'b?, {OPCODE_OP_IMM} };
|
||||
parameter logic [31:0] INSN_ORCB = { 12'b001010000111, 5'b? , 3'b101, 5'b?, {OPCODE_OP_IMM} };
|
||||
parameter logic [31:0] INSN_REV =
|
||||
{ 5'b01101, 2'b?, 5'b11111, 5'b? , 3'b101, 5'b?, {OPCODE_OP_IMM} };
|
||||
parameter logic [31:0] INSN_REV8 =
|
||||
{ 5'b01101, 2'b?, 5'b11000, 5'b? , 3'b101, 5'b?, {OPCODE_OP_IMM} };
|
||||
parameter logic [31:0] INSN_ORCB =
|
||||
{ 5'b00101, 2'b?, 5'b00111, 5'b? , 3'b101, 5'b?, {OPCODE_OP_IMM} };
|
||||
// ZBT
|
||||
parameter logic [31:0] INSN_FSRI = { 5'b?, 1'b1, 11'b?, 3'b101, 5'b?, {OPCODE_OP_IMM} };
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue