[DV/flow] Integrate with RISCV-DV (#446)

dv/uvm/Makefile

@@ -64,6 +64,10 @@ CSR_OPTS=--csr_yaml=${CSR_FILE} \
          --isa=${ISA} \
          --end_signature_addr=0x${SIGNATURE_ADDR}
 
+RISCV_DV_OPTS=--custom_target=${DV_DIR}/riscv_dv_extension \
+              --isa=${ISA} \
+              --mabi=ilp32 \
+
 # Generate random instructions
 .SILENT gen:
 	mkdir -p ${OUT}
@@ -73,9 +77,8 @@ CSR_OPTS=--csr_yaml=${CSR_FILE} \
      --steps=gen \
      --gen_timeout=${TIMEOUT} \
      --lsf_cmd="${LSF_CMD}" \
-     --core_setting_dir=${DV_DIR}/riscv_dv_extension \
-     --user_extension_dir=${DV_DIR}/riscv_dv_extension \
      --simulator=${SIMULATOR} \
+     ${RISCV_DV_OPTS} \
      ${COMMON_OPTS} \
      ${CSR_OPTS} \
      --sim_opts="+uvm_set_type_override=riscv_asm_program_gen,ibex_asm_program_gen \
@@ -89,8 +92,7 @@ gcc_compile:
      --steps=gcc_compile \
      ${COMMON_OPTS} \
      --gcc_opts=-mno-strict-align \
-     --isa=${ISA} \
-     --mabi=ilp32
+     ${RISCV_DV_OPTS} \
 
 # ISS simulation
 iss_sim:
@@ -100,8 +102,7 @@ iss_sim:
      --steps=iss_sim \
      ${COMMON_OPTS} \
      --iss=${ISS} \
-     --isa=${ISA} \
-     --core_setting_dir=${DV_DIR}/riscv_dv_extension \
+     ${RISCV_DV_OPTS} \
 
 # Compile ibex core TB
 compile:

dv/uvm/riscv_dv_extension/ibex_log_to_trace_csv.py

@@ -25,7 +25,7 @@ def process_ibex_sim_log(ibex_log, csv):
     ibex_instr = ""
 
     with open(ibex_log, "r") as f, open(csv, "w") as csv_fd:
-        trace_csv = RiscvInstructiontTraceCsv(csv_fd)
+        trace_csv = RiscvInstructionTraceCsv(csv_fd)
         trace_csv.start_new_trace()
         for line in f:
             if re.search("ecall", line):
@@ -36,7 +36,7 @@ def process_ibex_sim_log(ibex_log, csv):
                           ".*x(?P<rd>[1-9]\d*)=0x(?P<val>[0-9a-f]+)", line)
             if m:
                 # Write the extracted instruction to a csvcol buffer file
-                rv_instr_trace = RiscvInstructiontTraceEntry()
+                rv_instr_trace = RiscvInstructionTraceEntry()
                 rv_instr_trace.rd = gpr_to_abi("x%0s" % m.group("rd"))
                 rv_instr_trace.rd_val = m.group("val")
                 rv_instr_trace.addr = m.group("pc")

dv/uvm/riscv_dv_extension/riscvOVPsim.ic

@@ -1,6 +1,5 @@
 # riscOVPsim configuration file converted from YAML
---variant RV32I
---override riscvOVPsim/cpu/add_Extensions=MC
+--variant RV32IMC
 --override riscvOVPsim/cpu/misa_MXL=1
 --override riscvOVPsim/cpu/misa_MXL_mask=0x0 # 0
 --override riscvOVPsim/cpu/misa_Extensions_mask=0x0 # 0