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[syn] Use read_verilog -defer in yosys_run_synth.tcl

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Newer versions of sv2v carry through elaboration system tasks like
$fatal. ibex_top_tracing uses $fatal, but isn't actually used in the
syn_yosys flow. By using -defer, unused modules like ibex_top_tracing
are not elaborated in Yosys.
This commit is contained in:
Zachary Snow 2021-10-06 11:43:09 -06:00 • committed by Greg Chadwick
parent 873e2281cf
commit 0aa02b0f3f
1 changed files with 1 additions and 1 deletions
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2
syn/tcl/yosys_run_synth.tcl
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@ -14,7 +14,7 @@ if { $lr_synth_timing_run } {
write_sdc_out $lr_synth_sdc_file_in $lr_synth_sdc_file_out
}
yosys "read_verilog -sv ./rtl/prim_clock_gating.v $lr_synth_out_dir/generated/*.v"
yosys "read_verilog -defer -sv ./rtl/prim_clock_gating.v $lr_synth_out_dir/generated/*.v"
if { $lr_synth_ibex_branch_target_alu } {
yosys "chparam -set BranchTargetALU 1 $lr_synth_top_module"