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Adapt interrupt IF for Arty example, tracer and TB

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This commit is contained in:
Pirmin Vogel 2019-07-24 17:16:52 +01:00
parent 72c77f855d
commit 0dee0ff1ec
4 changed files with 20 additions and 21 deletions
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9
examples/fpga/artya7-100/rtl/top_artya7_100.sv
View file

@ -70,10 +70,11 @@ module top_artya7_100 (
.data_rdata_i (data_rdata),
.data_err_i ('b0),
.irq_i ('b0),
.irq_id_i ('b0),
.irq_ack_o (),
.irq_id_o (),
.irq_software_i (1'b0),
.irq_timer_i (1'b0),
.irq_external_i (1'b0),
.irq_fast_i (15'b0),
.irq_nm_i (1'b0),
.debug_req_i ('b0),

9
examples/sim/tb/ibex_tracing_tb.sv
View file

@ -100,10 +100,11 @@ module ibex_tracing_tb;
.data_err_i (1'b0),
// Interrupt inputs
.irq_i (1'b0),
.irq_id_i (5'b0),
.irq_ack_o (),
.irq_id_o (),
.irq_software_i (1'b0),
.irq_timer_i (1'b0),
.irq_external_i (1'b0),
.irq_fast_i (15'b0),
.irq_nm_i (1'b0),
// Debug Interface
.debug_req_i (1'b0),

3
rtl/ibex_core.sv
View file

@ -85,7 +85,6 @@ module ibex_core #(
output logic [31:0] rvfi_insn_uncompressed,
output logic rvfi_trap,
output logic rvfi_halt,
output logic rvfi_intr,
output logic [ 1:0] rvfi_mode,
output logic [ 4:0] rvfi_rs1_addr,
output logic [ 4:0] rvfi_rs2_addr,
@ -620,7 +619,6 @@ module ibex_core #(
if (!rst_ni) begin
rvfi_halt <= '0;
rvfi_trap <= '0;
rvfi_intr <= '0;
rvfi_order <= '0;
rvfi_insn <= '0;
rvfi_insn_uncompressed <= '0;
@ -642,7 +640,6 @@ module ibex_core #(
end else begin
rvfi_halt <= '0;
rvfi_trap <= illegal_insn_id;
rvfi_intr <= irq_ack_o;
rvfi_order <= rvfi_order + rvfi_valid;
rvfi_insn <= rvfi_insn_id;
rvfi_insn_uncompressed <= instr_rdata_id;

20
rtl/ibex_core_tracing.sv
View file

@ -44,10 +44,11 @@ module ibex_core_tracing #(
input logic data_err_i,
// Interrupt inputs
input logic irq_i, // level sensitive IR lines
input logic [4:0] irq_id_i,
output logic irq_ack_o, // irq ack
output logic [4:0] irq_id_o,
input logic irq_software_i,
input logic irq_timer_i,
input logic irq_external_i,
input logic [14:0] irq_fast_i,
input logic irq_nm_i, // non-maskeable interrupt
// Debug Interface
input logic debug_req_i,
@ -70,7 +71,6 @@ module ibex_core_tracing #(
logic [31:0] rvfi_insn_uncompressed;
logic rvfi_trap;
logic rvfi_halt;
logic rvfi_intr;
logic [ 1:0] rvfi_mode;
logic [ 4:0] rvfi_rs1_addr;
logic [ 4:0] rvfi_rs2_addr;
@ -119,10 +119,11 @@ module ibex_core_tracing #(
.data_rdata_i,
.data_err_i,
.irq_i,
.irq_id_i,
.irq_ack_o,
.irq_id_o,
.irq_software_i,
.irq_timer_i,
.irq_external_i,
.irq_fast_i,
.irq_nm_i,
.debug_req_i,
@ -132,7 +133,6 @@ module ibex_core_tracing #(
.rvfi_insn_uncompressed,
.rvfi_trap,
.rvfi_halt,
.rvfi_intr,
.rvfi_mode,
.rvfi_rs1_addr,
.rvfi_rs2_addr,