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https://github.com/openhwgroup/cve2.git
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Improve instruction tracer (added cycle count, formatting)
This commit is contained in:
Sven Stucki
parent
69b2473daa
commit
102691a06a
1 changed files with 31 additions and 21 deletions
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@ -800,6 +800,7 @@ module riscv_core
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`ifdef TRACE_EXECUTION
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integer f;
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string fn;
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integer cycles;
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logic [31:0] instr;
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logic compressed;
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logic [31:0] pc;
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@ -811,10 +812,12 @@ module riscv_core
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// open/close output file for writing
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initial
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begin
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#1
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#1 // delay needed for valid core_id_i
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$sformat(fn, "trace_core_%h.log", core_id_i);
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$display("Output file: %s", fn);
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$display("[TRACER] Output filename is: %s", fn);
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f = $fopen(fn, "w");
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$fwrite(f, "%19s\t%6s\t%10s\t%10s\t \t%s\n", "Time", "Cycles", "PC", "Instr", "Mnemonic");
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//$fwrite(f, "Time\tCycles\tPC\tInstruction\n");
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end
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final
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@ -825,8 +828,6 @@ module riscv_core
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// log execution
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always @(posedge clk)
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begin
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#1
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// get current PC and instruction
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instr = id_stage_i.instr[31:0];
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compressed = id_stage_i.compressed_instr_o;
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@ -835,21 +836,20 @@ module riscv_core
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// get register values
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rd = instr[`REG_D];
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rs1 = instr[`REG_S1];
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rs1_value = id_stage_i.operand_a_fw_id; //r[rs1];
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rs1_value = id_stage_i.operand_a_fw_id;
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rs2 = instr[`REG_S2];
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rs2_value = id_stage_i.operand_b_fw_id; //r[rs2];
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rs2_value = id_stage_i.operand_b_fw_id;
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if (id_stage_i.stall_id_o == 1'b0 && id_stage_i.controller_i.ctrl_fsm_cs == id_stage_i.controller_i.DECODE)
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begin
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mnemonic = "";
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imm = 0;
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$fwrite(f, "%t:\t0x%h\t0x%h\t", $time, pc, instr);
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$fwrite(f, "%t\t%6d\t0x%h\t", $time, cycles, pc);
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if (compressed)
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//$fwrite(f, "C (0x%4h)\t", id_stage_i.instr_rdata_i[15:0]);
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$fwrite(f, "C\t");
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$fwrite(f, "0x %4h\tC\t", id_stage_i.instr_rdata_i[15:0]);
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else
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$fwrite(f, "I\t");
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$fwrite(f, "0x%h\tI\t", instr);
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// use casex instead of case inside due to ModelSim bug
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casex (instr)
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@ -931,22 +931,32 @@ module riscv_core
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`INSTR_MULHSU: printRInstr("MULHSU");
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`INSTR_MULHU: printRInstr("MULHU");
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*/
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default: printMnemonic("Unknown instruction");
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default: printMnemonic("INVALID");
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endcase // unique case (instr)
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$fflush(f);
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end
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end // always @ (posedge clk)
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always_ff @(posedge clk, negedge rst_n)
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begin
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if (rst_n == 1'b0)
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cycles = 0;
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else
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cycles = cycles + 1;
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end
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function void printMnemonic(input string mnemonic);
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begin
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riscv_core.mnemonic = mnemonic;
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$fdisplay(f, "%s", mnemonic);
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$fdisplay(f, "%7s", mnemonic);
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end
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endfunction // printMnemonic
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function void printRInstr(input string mnemonic);
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begin
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riscv_core.mnemonic = mnemonic;
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$fdisplay(f, "%s\tx%0d, x%0d (0x%h), x%0d (0x%h)", mnemonic,
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$fdisplay(f, "%7s\tx%0d, x%0d (0x%h), x%0d (0x%h)", mnemonic,
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rd, rs1, rs1_value, rs2, rs2_value);
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end
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endfunction // printRInstr
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@ -955,7 +965,7 @@ module riscv_core
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begin
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riscv_core.mnemonic = mnemonic;
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imm = id_stage_i.imm_i_type;
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$fdisplay(f, "%s\tx%0d, x%0d (0x%h), 0x%0h (imm)", mnemonic,
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$fdisplay(f, "%7s\tx%0d, x%0d (0x%h), 0x%0h (imm)", mnemonic,
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rd, rs1, rs1_value, imm);
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end
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endfunction // printIInstr
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@ -964,7 +974,7 @@ module riscv_core
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begin
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riscv_core.mnemonic = mnemonic;
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imm = id_stage_i.imm_i_type;
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$fdisplay(f, "%s\tx%0d, x%0d (0x%h), 0x%0h (imm) (-> 0x%h)", mnemonic,
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$fdisplay(f, "%7s\tx%0d, x%0d (0x%h), 0x%0h (imm) (-> 0x%h)", mnemonic,
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rd, rs1, rs1_value, imm, imm+rs1_value);
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end
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endfunction // printILInstr
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@ -973,7 +983,7 @@ module riscv_core
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begin
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riscv_core.mnemonic = mnemonic;
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imm = id_stage_i.imm_s_type;
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$fdisplay(f, "%s\tx%0d (0x%h), x%0d (0x%h), 0x%0h (imm) (-> 0x%h)", mnemonic,
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$fdisplay(f, "%7s\tx%0d (0x%h), x%0d (0x%h), 0x%0h (imm) (-> 0x%h)", mnemonic,
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rs1, rs1_value, rs2, rs2_value, imm, imm+rs1_value);
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end
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endfunction // printSInstr
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@ -982,7 +992,7 @@ module riscv_core
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begin
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riscv_core.mnemonic = mnemonic;
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imm = id_stage_i.imm_sb_type;
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$fdisplay(f, "%s\tx%0d (0x%h), x%0d (0x%h), 0x%0h (-> 0x%h)", mnemonic,
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$fdisplay(f, "%7s\tx%0d (0x%h), x%0d (0x%h), 0x%0h (-> 0x%h)", mnemonic,
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rs1, rs1_value, rs2, rs2_value, imm, imm+pc);
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end
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endfunction // printSBInstr
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@ -991,14 +1001,14 @@ module riscv_core
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begin
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riscv_core.mnemonic = mnemonic;
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imm = id_stage_i.imm_uj_type;
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$fdisplay(f, "%s\tx%0d, 0x%h (-> 0x%h)", mnemonic, rd, imm, imm+pc);
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$fdisplay(f, "%7s\tx%0d, 0x%h (-> 0x%h)", mnemonic, rd, imm, imm+pc);
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end
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endfunction // printUJInstr
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function void printRDInstr(input string mnemonic);
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begin
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riscv_core.mnemonic = mnemonic;
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$fdisplay(f, "%s\tx%0d", mnemonic, rd);
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$fdisplay(f, "%7s\tx%0d", mnemonic, rd);
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end
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endfunction // printRDInstr
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@ -1010,10 +1020,10 @@ module riscv_core
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csr = instr[31:20];
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if (instr[14] == 1'b0) begin
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$fdisplay(f, "%s\tx%0d, 0x%h (csr), x%0d (0x%h)", mnemonic, rd, csr,
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$fdisplay(f, "%7s\tx%0d, 0x%h (csr), x%0d (0x%h)", mnemonic, rd, csr,
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rs1, rs1_value);
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end else begin
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$fdisplay(f, "%s\tx%0d, 0x%h (csr), 0x%h (imm)", mnemonic, rd, csr, imm);
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$fdisplay(f, "%7s\tx%0d, 0x%h (csr), 0x%h (imm)", mnemonic, rd, csr, imm);
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end
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end
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endfunction // printCSRInstr
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