fix verilator .core (#116)

* fix top and sec

* fix .core

Makefile

@@ -52,7 +52,7 @@ run-simple-system: sw-simple-hello | $(Vcve2_simple_system)
 		--raminit=$(simple-system-program)
 
 compile_verilator:
-	fusesoc --cores-root . run --no-export --target=lint --tool=verilator --setup --build lowrisc:cve2:cve2_top:0.1 2>&1 | tee buildsim.log
+	fusesoc --cores-root . run --no-export --target=lint --tool=verilator --setup --build openhwgroup:cve2:cve2_top:0.1 2>&1 | tee buildsim.log
 
 # Arty A7 FPGA example
 # Use the following targets (depending on your hardware):

cve2_core.core

@@ -2,16 +2,14 @@ CAPI=2:
 # Copyright lowRISC contributors.
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:cve2:cve2_core:0.1"
+name: "openhwgroup:cve2:cve2_core:0.1"
 description: "Ibex CPU Core Components"
 
 filesets:
   files_rtl:
     depend:
       - lowrisc:prim:assert
-      - lowrisc:prim:clock_gating
-      - lowrisc:prim:lfsr
-      - lowrisc:cve2:cve2_pkg
+      - openhwgroup:cve2:cve2_pkg
       - lowrisc:dv:dv_fcov_macros
     files:
       - rtl/cve2_alu.sv
@@ -80,68 +78,12 @@ parameters:
     paramtype: vlogdefine
     description: "Bitmanip implementation parameter enum. See the cve2_pkg::rv32b_e enum in cve2_pkg.sv for permitted values."
 
-  RegFile:
-    datatype: str
-    default: cve2_pkg::RegFileFF
-    paramtype: vlogdefine
-    description: "Register file implementation parameter enum. See the cve2_pkg::regfile_e enum in cve2_pkg.sv for permitted values."
-
-  ICache:
-    datatype: int
-    default: 0
-    paramtype: vlogparam
-    description: "Enable instruction cache"
-
-  ICacheECC:
-    datatype: int
-    default: 0
-    paramtype: vlogparam
-    description: "Enable ECC protection in instruction cache"
-
-  WritebackStage:
-    datatype: int
-    default: 0
-    paramtype: vlogparam
-    description: "Enables third pipeline stage (EXPERIMENTAL) [0/1]"
-
-  BranchPredictor:
-    datatype: int
-    paramtype: vlogparam
-    default: 0
-    description: "Enables static branch prediction (EXPERIMENTAL)"
-
-  SecureCVE2:
-    datatype: int
-    default: 0
-    paramtype: vlogparam
-    description: "Enables security hardening features (EXPERIMENTAL) [0/1]"
-
-  PMPEnable:
-    datatype: int
-    default: 0
-    paramtype: vlogparam
-    description: "Enable PMP"
-
-  PMPGranularity:
-    datatype: int
-    default: 0
-    paramtype: vlogparam
-    description: "Granularity of NAPOT range, 0 = 4 byte, 1 = byte, 2 = 16 byte, 3 = 32 byte etc"
-
-  PMPNumRegions:
-    datatype: int
-    default: 4
-    paramtype: vlogparam
-    description: "Number of PMP regions"
-
 targets:
   default: &default_target
     filesets:
       - tool_verilator ? (files_lint_verilator)
       - tool_veriblelint ? (files_lint_verible)
       - files_rtl
-      - target_sim? (files_clk_gate)
-      - files_check_tool_requirements
     toplevel: cve2_core
     parameters:
       - tool_vivado ? (FPGA_XILINX=true)

cve2_pkg.core

@@ -2,7 +2,7 @@ CAPI=2:
 # Copyright lowRISC contributors.
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:cve2:cve2_pkg:0.1"
+name: "openhwgroup:cve2:cve2_pkg:0.1"
 description: "Header package for CVE2"
 
 filesets:

cve2_top.core

@@ -2,14 +2,14 @@ CAPI=2:
 # Copyright lowRISC contributors.
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:cve2:cve2_top:0.1"
+name: "openhwgroup:cve2:cve2_top:0.1"
 description: "Ibex, a small RV32 CPU core"
 
 filesets:
   files_rtl:
     depend:
-      - lowrisc:cve2:cve2_pkg
-      - lowrisc:cve2:cve2_core
+      - openhwgroup:cve2:cve2_pkg
+      - openhwgroup:cve2:cve2_core
       - lowrisc:prim:buf
       - lowrisc:prim:clock_mux2
       - lowrisc:prim:flop
@@ -33,7 +33,7 @@ filesets:
 
   files_clk_gate:
     files:
-    - bhv/cve2_sim_clock_gate.sv
+      - bhv/cve2_sim_clock_gate.sv
     file_type: systemVerilogSource
 
 parameters:
@@ -68,65 +68,6 @@ parameters:
     paramtype: vlogdefine
     description: "Bitmanip implementation parameter enum. See the cve2_pkg::rv32b_e enum in cve2_pkg.sv for permitted values."
 
-  RegFile:
-    datatype: str
-    default: cve2_pkg::RegFileFF
-    paramtype: vlogdefine
-    description: "Register file implementation parameter enum. See the cve2_pkg::regfile_e enum in cve2_pkg.sv for permitted values."
-
-  ICache:
-    datatype: int
-    default: 0
-    paramtype: vlogparam
-    description: "Enable instruction cache"
-
-  ICacheECC:
-    datatype: int
-    default: 0
-    paramtype: vlogparam
-    description: "Enable ECC protection in instruction cache"
-
-  WritebackStage:
-    datatype: int
-    default: 0
-    paramtype: vlogparam
-    description: "Enables third pipeline stage (EXPERIMENTAL) [0/1]"
-
-  BranchPredictor:
-    datatype: int
-    paramtype: vlogparam
-    default: 0
-    description: "Enables static branch prediction (EXPERIMENTAL)"
-
-  SecureCVE2:
-    datatype: int
-    default: 0
-    paramtype: vlogparam
-    description: "Enables security hardening features (EXPERIMENTAL) [0/1]"
-
-  ICacheScramble:
-    datatype: int
-    default: 0
-    paramtype: vlogparam
-    description: "Enables ICache scrambling feature (EXPERIMENTAL) [0/1]"
-
-  PMPEnable:
-    datatype: int
-    default: 0
-    paramtype: vlogparam
-    description: "Enable PMP"
-
-  PMPGranularity:
-    datatype: int
-    default: 0
-    paramtype: vlogparam
-    description: "Granularity of NAPOT range, 0 = 4 byte, 1 = byte, 2 = 16 byte, 3 = 32 byte etc"
-
-  PMPNumRegions:
-    datatype: int
-    default: 4
-    paramtype: vlogparam
-    description: "Number of PMP regions"
 
 targets:
   default: &default_target
@@ -134,11 +75,11 @@ targets:
       - tool_verilator ? (files_lint_verilator)
       - tool_veriblelint ? (files_lint_verible)
       - files_rtl
-      - target_sim? (files_clk_gate)
-      - files_check_tool_requirements
+      - target_sim ? (files_clk_gate)
     toplevel: cve2_top
     parameters:
       - tool_vivado ? (FPGA_XILINX=true)
+
   lint:
     <<: *default_target
     parameters:

rtl/cve2_core.sv

@@ -709,7 +709,7 @@ module cve2_core import cve2_pkg::*; #(
   cve2_register_file_ff #(
     .RV32E            (RV32E),
     .DataWidth        (32),
-    .WordZeroVal      (32'(prim_secded_pkg::SecdedInv3932ZeroWord))
+    .WordZeroVal      (32'0)
   ) register_file_i (
     .clk_i (clk_i),
     .rst_ni(rst_ni),