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[rtl, bitmanip] Align Zbb implementation with draft v.0.93 and v.1.0.0
This invovles the following changes: - Rename pcnt to cpop - Switch encoding of max and minu - Remove rev from Balanced version, only available in Full version via grev (Zbp) - Include sext.b/h (previously in Zb_tmp) - Remove slo[i] and sro[i] from Balanced version, only available in Full version (Zbp) Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
This commit is contained in:
Pirmin Vogel
parent
e765b4dfec
commit
16d6f5ea2b
6 changed files with 46 additions and 48 deletions
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@ -97,8 +97,6 @@ Bit Manipulation Extension
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+---------------------------------+---------------+--------------------------+
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| Zbt (Ternary) | Balanced/Full | All |
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+---------------------------------+---------------+--------------------------+
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| Zb_tmp (Temporary) [#B_zb_tmp]_ | Balanced/Full | None |
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+---------------------------------+---------------+--------------------------+
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The implementation of the B-extension comes with an area overhead of 1.8 to 3.0 kGE for the balanced version and 6.0 to 8.7 kGE for the full version.
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That corresponds to an approximate percentage increase in area of 9 to 14 % and 25 to 30 % for the balanced and full versions respectively.
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@ -178,6 +176,3 @@ See :ref:`load-store-unit` for more details.
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Ibex will be updated to match future versions of the specification.
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Prior to ratification this may involve backwards incompatible changes.
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Additionally, neither GCC or Clang have committed to maintaining support upstream for unratified versions of the specification.
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.. [#B_zb_tmp] The sign-extend instructions `sext.b/sext.h` are defined but not unambiguously categorized in draft version 0.92 of the extension.
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Temporarily, they have been assigned a separate Z-extension (Zb_tmp) both in Ibex and the RISCV-DV random instruction generator used to verify the bit manipulation instructions in Ibex.
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@ -304,7 +304,7 @@ module ibex_alu #(
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always_comb begin
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unique case (operator_i)
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ALU_SLL: shift_left = 1'b1;
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ALU_SLO,
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ALU_SLO: shift_left = (RV32B == RV32BFull) ? 1'b1 : 1'b0;
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ALU_BFP: shift_left = (RV32B != RV32BNone) ? 1'b1 : 1'b0;
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ALU_ROL: shift_left = (RV32B != RV32BNone) ? instr_first_cycle_i : 0;
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ALU_ROR: shift_left = (RV32B != RV32BNone) ? ~instr_first_cycle_i : 0;
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@ -321,7 +321,7 @@ module ibex_alu #(
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assign shift_arith = (operator_i == ALU_SRA);
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assign shift_ones =
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(RV32B != RV32BNone) ? (operator_i == ALU_SLO) | (operator_i == ALU_SRO) : 1'b0;
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(RV32B == RV32BFull) ? (operator_i == ALU_SLO) | (operator_i == ALU_SRO) : 1'b0;
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assign shift_funnel =
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(RV32B != RV32BNone) ? (operator_i == ALU_FSL) | (operator_i == ALU_FSR) : 1'b0;
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@ -417,7 +417,7 @@ module ibex_alu #(
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// The bit-counter structure computes the number of set bits in its operand. Partial results
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// (from left to right) are needed to compute the control masks for computation of
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// bcompress/bdecompress by the butterfly network, if implemented.
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// For pcnt, clz and ctz, only the end result is used.
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// For cpop, clz and ctz, only the end result is used.
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logic zbe_op;
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logic bitcnt_ctz;
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@ -458,7 +458,7 @@ module ibex_alu #(
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case (1'b1)
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zbe_op: bitcnt_bits = operand_b_i;
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bitcnt_cz: bitcnt_bits = bitcnt_bit_mask & ~bitcnt_mask_op; // clz / ctz
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default: bitcnt_bits = operand_a_i; // pcnt
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default: bitcnt_bits = operand_a_i; // cpop
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endcase
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end
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@ -591,16 +591,16 @@ module ibex_alu #(
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// General Reverse and Or-combine //
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////////////////////////////////////
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// Only a subset of the General reverse and or-combine instructions are implemented in the
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// balanced version of the B extension. Currently rev, rev8 and orc.b are supported in the
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// base extension.
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// Only a subset of the general reverse and or-combine instructions are implemented in the
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// balanced version of the B extension. Currently rev8 (shift_amt = 5'b11000) and orc.b
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// (shift_amt = 5'b00111) are supported in the base extension.
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logic [4:0] zbp_shift_amt;
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logic gorc_op;
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assign gorc_op = (operator_i == ALU_GORC);
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assign zbp_shift_amt[2:0] = (RV32B == RV32BFull) ? shift_amt[2:0] : {3{&shift_amt[2:0]}};
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assign zbp_shift_amt[4:3] = (RV32B == RV32BFull) ? shift_amt[4:3] : {2{&shift_amt[4:3]}};
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assign zbp_shift_amt[2:0] = (RV32B == RV32BFull) ? shift_amt[2:0] : {3{shift_amt[0]}};
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assign zbp_shift_amt[4:3] = (RV32B == RV32BFull) ? shift_amt[4:3] : {2{shift_amt[3]}};
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always_comb begin
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rev_result = operand_a_i;
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@ -1250,7 +1250,7 @@ module ibex_alu #(
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// Bitcount Operations (RV32B)
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ALU_CLZ, ALU_CTZ,
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ALU_PCNT: result_o = {26'h0, bitcnt_result};
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ALU_CPOP: result_o = {26'h0, bitcnt_result};
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// Pack Operations (RV32B)
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ALU_PACK, ALU_PACKH,
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@ -362,7 +362,7 @@ module ibex_decoder #(
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3'b001: begin
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unique case (instr[31:27])
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5'b0_0000: illegal_insn = (instr[26:25] == 2'b00) ? 1'b0 : 1'b1; // slli
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5'b0_0100, // sloi
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5'b0_0100: illegal_insn = (RV32B == RV32BFull) ? 1'b0 : 1'b1; // sloi
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5'b0_1001, // bclri
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5'b0_0101, // bseti
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5'b0_1101: illegal_insn = (RV32B != RV32BNone) ? 1'b0 : 1'b1; // binvi
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@ -375,7 +375,7 @@ module ibex_decoder #(
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unique case(instr[26:20])
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7'b000_0000, // clz
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7'b000_0001, // ctz
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7'b000_0010, // pcnt
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7'b000_0010, // cpop
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7'b000_0100, // sext.b
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7'b000_0101: illegal_insn = (RV32B != RV32BNone) ? 1'b0 : 1'b1; // sext.h
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7'b001_0000, // crc32.b
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@ -400,20 +400,17 @@ module ibex_decoder #(
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5'b0_0000, // srli
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5'b0_1000: illegal_insn = (instr[26:25] == 2'b00) ? 1'b0 : 1'b1; // srai
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5'b0_0100, // sroi
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5'b0_0100: illegal_insn = (RV32B == RV32BFull) ? 1'b0 : 1'b1; // sroi
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5'b0_1100, // rori
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5'b0_1001: illegal_insn = (RV32B != RV32BNone) ? 1'b0 : 1'b1; // bexti
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5'b0_1101: begin
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if ((RV32B == RV32BFull)) begin
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illegal_insn = 1'b0; // grevi
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end else if (RV32B == RV32BBalanced) begin
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illegal_insn = (instr[24:20] == 5'b11000) ? 1'b0 : 1'b1; // rev8
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end else begin
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unique case (instr[24:20])
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5'b11111, // rev
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5'b11000: illegal_insn = (RV32B == RV32BBalanced) ? 1'b0 : 1'b1; // rev8
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default: illegal_insn = 1'b1;
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endcase
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illegal_insn = 1'b1;
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end
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end
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5'b0_0101: begin
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@ -470,13 +467,11 @@ module ibex_decoder #(
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{7'b010_0000, 3'b111}, // andn
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{7'b010_0000, 3'b110}, // orn
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{7'b010_0000, 3'b100}, // xnor
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{7'b001_0000, 3'b001}, // slo
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{7'b001_0000, 3'b101}, // sro
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{7'b011_0000, 3'b001}, // rol
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{7'b011_0000, 3'b101}, // ror
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{7'b000_0101, 3'b100}, // min
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{7'b000_0101, 3'b101}, // max
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{7'b000_0101, 3'b110}, // minu
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{7'b000_0101, 3'b110}, // max
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{7'b000_0101, 3'b101}, // minu
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{7'b000_0101, 3'b111}, // maxu
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{7'b000_0100, 3'b100}, // pack
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{7'b010_0100, 3'b100}, // packu
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@ -496,6 +491,8 @@ module ibex_decoder #(
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{7'b001_0100, 3'b101}, // gorc
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{7'b000_0100, 3'b001}, // shfl
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{7'b000_0100, 3'b101}, // unshfl
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{7'b001_0000, 3'b001}, // slo
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{7'b001_0000, 3'b101}, // sro
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// RV32B zbc
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{7'b000_0101, 3'b001}, // clmul
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{7'b000_0101, 3'b010}, // clmulr
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@ -823,7 +820,8 @@ module ibex_decoder #(
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if (RV32B != RV32BNone) begin
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unique case (instr_alu[31:27])
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5'b0_0000: alu_operator_o = ALU_SLL; // Shift Left Logical by Immediate
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5'b0_0100: alu_operator_o = ALU_SLO; // Shift Left Ones by Immediate
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// Shift Left Ones by Immediate
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5'b0_0100: if (RV32B == RV32BFull) alu_operator_o = ALU_SLO;
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5'b0_1001: alu_operator_o = ALU_BCLR; // Clear bit specified by immediate
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5'b0_0101: alu_operator_o = ALU_BSET; // Set bit specified by immediate
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5'b0_1101: alu_operator_o = ALU_BINV; // Invert bit specified by immediate.
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@ -833,7 +831,7 @@ module ibex_decoder #(
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unique case (instr_alu[26:20])
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7'b000_0000: alu_operator_o = ALU_CLZ; // clz
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7'b000_0001: alu_operator_o = ALU_CTZ; // ctz
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7'b000_0010: alu_operator_o = ALU_PCNT; // pcnt
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7'b000_0010: alu_operator_o = ALU_CPOP; // cpop
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7'b000_0100: alu_operator_o = ALU_SEXTB; // sext.b
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7'b000_0101: alu_operator_o = ALU_SEXTH; // sext.h
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7'b001_0000: begin
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@ -897,7 +895,8 @@ module ibex_decoder #(
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unique case (instr_alu[31:27])
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5'b0_0000: alu_operator_o = ALU_SRL; // Shift Right Logical by Immediate
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5'b0_1000: alu_operator_o = ALU_SRA; // Shift Right Arithmetically by Immediate
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5'b0_0100: alu_operator_o = ALU_SRO; // Shift Right Ones by Immediate
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// Shift Right Ones by Immediate
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5'b0_0100: if (RV32B == RV32BFull) alu_operator_o = ALU_SRO;
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5'b0_1001: alu_operator_o = ALU_BEXT; // Extract bit specified by immediate.
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5'b0_1100: begin
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alu_operator_o = ALU_ROR; // Rotate Right by Immediate
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@ -989,8 +988,6 @@ module ibex_decoder #(
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{7'b010_0000, 3'b101}: alu_operator_o = ALU_SRA; // Shift Right Arithmetic
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// RV32B ALU Operations
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{7'b001_0000, 3'b001}: if (RV32B != RV32BNone) alu_operator_o = ALU_SLO; // slo
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{7'b001_0000, 3'b101}: if (RV32B != RV32BNone) alu_operator_o = ALU_SRO; // sro
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{7'b011_0000, 3'b001}: begin
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if (RV32B != RV32BNone) begin
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alu_operator_o = ALU_ROL; // rol
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@ -1005,8 +1002,8 @@ module ibex_decoder #(
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end
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{7'b000_0101, 3'b100}: if (RV32B != RV32BNone) alu_operator_o = ALU_MIN; // min
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{7'b000_0101, 3'b101}: if (RV32B != RV32BNone) alu_operator_o = ALU_MAX; // max
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{7'b000_0101, 3'b110}: if (RV32B != RV32BNone) alu_operator_o = ALU_MINU; // minu
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{7'b000_0101, 3'b110}: if (RV32B != RV32BNone) alu_operator_o = ALU_MAX; // max
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{7'b000_0101, 3'b101}: if (RV32B != RV32BNone) alu_operator_o = ALU_MINU; // minu
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{7'b000_0101, 3'b111}: if (RV32B != RV32BNone) alu_operator_o = ALU_MAXU; // maxu
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{7'b000_0100, 3'b100}: if (RV32B != RV32BNone) alu_operator_o = ALU_PACK; // pack
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@ -1036,6 +1033,8 @@ module ibex_decoder #(
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{7'b001_0100, 3'b101}: if (RV32B != RV32BNone) alu_operator_o = ALU_GORC; // grev
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{7'b000_0100, 3'b001}: if (RV32B == RV32BFull) alu_operator_o = ALU_SHFL; // shfl
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{7'b000_0100, 3'b101}: if (RV32B == RV32BFull) alu_operator_o = ALU_UNSHFL; // unshfl
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{7'b001_0000, 3'b001}: if (RV32B == RV32BFull) alu_operator_o = ALU_SLO; // slo
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{7'b001_0000, 3'b101}: if (RV32B == RV32BFull) alu_operator_o = ALU_SRO; // sro
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// RV32B zbc
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{7'b000_0101, 3'b001}: if (RV32B == RV32BFull) alu_operator_o = ALU_CLMUL; // clmul
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@ -135,7 +135,7 @@ package ibex_pkg;
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// RV32B
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ALU_CLZ,
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ALU_CTZ,
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ALU_PCNT,
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ALU_CPOP,
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// Set lower than
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ALU_SLT,
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@ -912,11 +912,7 @@ module ibex_tracer (
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INSN_SH2ADD: decode_r_insn("sh2add");
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INSN_SH3ADD: decode_r_insn("sh3add");
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// RV32B - ZBB
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INSN_SLOI: decode_i_shift_insn("sloi");
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INSN_SROI: decode_i_shift_insn("sroi");
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INSN_RORI: decode_i_shift_insn("rori");
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INSN_SLO: decode_r_insn("slo");
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INSN_SRO: decode_r_insn("sro");
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INSN_ROL: decode_r_insn("rol");
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INSN_ROR: decode_r_insn("ror");
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INSN_MIN: decode_r_insn("min");
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@ -940,7 +936,7 @@ module ibex_tracer (
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INSN_PACKU: decode_r_insn("packu");
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INSN_CLZ: decode_r1_insn("clz");
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INSN_CTZ: decode_r1_insn("ctz");
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INSN_PCNT: decode_r1_insn("pcnt");
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INSN_CPOP: decode_r1_insn("cpop");
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INSN_SEXTB: decode_r1_insn("sext.b");
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INSN_SEXTH: decode_r1_insn("sext.h");
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// RV32B - ZBS
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@ -1030,6 +1026,10 @@ module ibex_tracer (
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default: decode_i_insn("unshfli");
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endcase
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end
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INSN_SLO: decode_r_insn("slo");
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INSN_SRO: decode_r_insn("sro");
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INSN_SLOI: decode_i_shift_insn("sloi");
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INSN_SROI: decode_i_shift_insn("sroi");
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// RV32B - ZBT
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INSN_CMIX: decode_r_cmixcmov_insn("cmix");
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@ -77,15 +77,13 @@ package ibex_tracer_pkg;
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parameter logic [31:0] INSN_SH3ADD = { 7'b0010000, 10'h?, 3'b110, 5'h?, {OPCODE_OP} };
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// ZBB
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parameter logic [31:0] INSN_SLOI = { 5'b00100 , 12'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} };
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// Only log2(XLEN) bits of the immediate are used. For RV32, this means only the bits in
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// instr[24:20] are effectively used. Whenever instr[26] is set, sroi/rori is instead decoded as
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// fsri.
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parameter logic [31:0] INSN_SROI = { 5'b00100 , 1'b0, 11'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSN_RORI = { 5'b01100 , 1'b0, 11'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSN_CLZ = { 12'b011000000000, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSN_CTZ = { 12'b011000000001, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSN_PCNT = { 12'b011000000010, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSN_CPOP = { 12'b011000000010, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSN_SEXTB = { 12'b011000000100, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSN_SEXTH = { 12'b011000000101, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} };
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// The ZEXT.B and ZEXT.H pseudo-instructions are currently not emitted by the tracer due to a lack
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@ -96,13 +94,11 @@ package ibex_tracer_pkg;
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// sext -- pseudoinstruction: pack rd, rs zero
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// parameter logic [31:0] INSN_ZEXTH = { 7'b0000100, 5'b00000, 5'h?, 3'b100, 5'h?, {OPCODE_OP} };
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parameter logic [31:0] INSN_SLO = { 7'b0010000, 10'h?, 3'b001, 5'h?, {OPCODE_OP} };
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parameter logic [31:0] INSN_SRO = { 7'b0010000, 10'h?, 3'b101, 5'h?, {OPCODE_OP} };
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parameter logic [31:0] INSN_ROL = { 7'b0110000, 10'h?, 3'b001, 5'h?, {OPCODE_OP} };
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parameter logic [31:0] INSN_ROR = { 7'b0110000, 10'h?, 3'b101, 5'h?, {OPCODE_OP} };
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parameter logic [31:0] INSN_MIN = { 7'b0000101, 10'h?, 3'b100, 5'h?, {OPCODE_OP} };
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parameter logic [31:0] INSN_MAX = { 7'b0000101, 10'h?, 3'b101, 5'h?, {OPCODE_OP} };
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parameter logic [31:0] INSN_MINU = { 7'b0000101, 10'h?, 3'b110, 5'h?, {OPCODE_OP} };
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parameter logic [31:0] INSN_MAX = { 7'b0000101, 10'h?, 3'b110, 5'h?, {OPCODE_OP} };
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parameter logic [31:0] INSN_MINU = { 7'b0000101, 10'h?, 3'b101, 5'h?, {OPCODE_OP} };
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parameter logic [31:0] INSN_MAXU = { 7'b0000101, 10'h?, 3'b111, 5'h?, {OPCODE_OP} };
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parameter logic [31:0] INSN_XNOR = { 7'b0100000, 10'h?, 3'b100, 5'h?, {OPCODE_OP} };
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parameter logic [31:0] INSN_ORN = { 7'b0100000, 10'h?, 3'b110, 5'h?, {OPCODE_OP} };
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@ -247,6 +243,14 @@ package ibex_tracer_pkg;
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parameter logic [31:0] INSN_SHFL = { 7'b0000100, 10'h?, 3'b001, 5'h?, {OPCODE_OP} };
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parameter logic [31:0] INSN_UNSHFL = { 7'b0000100, 10'h?, 3'b101, 5'h?, {OPCODE_OP} };
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parameter logic [31:0] INSN_SLO = { 7'b0010000, 10'h?, 3'b001, 5'h?, {OPCODE_OP} };
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||||
parameter logic [31:0] INSN_SRO = { 7'b0010000, 10'h?, 3'b101, 5'h?, {OPCODE_OP} };
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||||
parameter logic [31:0] INSN_SLOI = { 5'b00100 , 12'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} };
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// Only log2(XLEN) bits of the immediate are used. For RV32, this means only the bits in
|
||||
// instr[24:20] are effectively used. Whenever instr[26] is set, sroi/rori is instead decoded as
|
||||
// fsri.
|
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parameter logic [31:0] INSN_SROI = { 5'b00100 , 1'b0, 11'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} };
|
||||
|
||||
// ZBE
|
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parameter logic [31:0] INSN_BDECOMPRESS = {7'b0100100, 10'h?, 3'b110, 5'h?, {OPCODE_OP} };
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parameter logic [31:0] INSN_BCOMPRESS = {7'b0000100, 10'h?, 3'b110, 5'h?, {OPCODE_OP} };
|
||||
|
|
|
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Loading…
Add table
Add a link
Reference in a new issue