Linting

alu.sv

@@ -331,7 +331,7 @@ module riscv_alu
   begin
     cmp_signed = 4'b0;
 
-    case (operator_i)
+    unique case (operator_i)
       `ALU_GTS,
       `ALU_GES,
       `ALU_LTS,
@@ -347,6 +347,8 @@ module riscv_alu
           default:     cmp_signed[3:0] = 4'b1000;
         endcase
       end
+
+      default:;
     endcase
   end
 
@@ -576,7 +578,7 @@ module riscv_alu
       end
 
       `ALU_SHUF2: begin
-        case (vector_mode_i)
+        unique case (vector_mode_i)
           `VEC_MODE8: begin
             shuffle_reg_sel[3] = operand_b_i[26];
             shuffle_reg_sel[2] = operand_b_i[18];
@@ -590,6 +592,8 @@ module riscv_alu
             shuffle_reg_sel[1] = operand_b_i[ 1];
             shuffle_reg_sel[0] = operand_b_i[ 1];
           end
+
+          default:;
         endcase
       end
 
@@ -601,7 +605,7 @@ module riscv_alu
       `ALU_PCKLO,
       `ALU_PCKHI: begin
 
-        case (vector_mode_i)
+        unique case (vector_mode_i)
           `VEC_MODE8: begin
             shuffle_byte_sel[3] = 2'b00;
             shuffle_byte_sel[2] = 2'b00;
@@ -615,12 +619,14 @@ module riscv_alu
             shuffle_byte_sel[1] = 2'b01;
             shuffle_byte_sel[0] = 2'b00;
           end
+
+          default:;
         endcase
       end
 
       `ALU_SHUF2,
       `ALU_SHUF: begin
-        case (vector_mode_i)
+        unique case (vector_mode_i)
           `VEC_MODE8: begin
             shuffle_byte_sel[3] = operand_b_i[25:24];
             shuffle_byte_sel[2] = operand_b_i[17:16];
@@ -634,6 +640,8 @@ module riscv_alu
             shuffle_byte_sel[1] = {operand_b_i[ 0], 1'b1};
             shuffle_byte_sel[0] = {operand_b_i[ 0], 1'b0};
           end
+
+          default:;
         endcase
       end
 
@@ -999,36 +1007,36 @@ module alu_popcnt
   output logic [5: 0]  result_o
 );
 
-  logic [1:0]  cnt_l1[16];
-  logic [2:0]  cnt_l2[8];
-  logic [3:0]  cnt_l3[4];
-  logic [4:0]  cnt_l4[2];
+  logic [15:0][1:0] cnt_l1;
+  logic [ 7:0][2:0] cnt_l2;
+  logic [ 3:0][3:0] cnt_l3;
+  logic [ 1:0][4:0] cnt_l4;
 
   genvar      l, m, n, p;
   generate for(l = 0; l < 16; l++)
     begin
-      assign cnt_l1[l] = in_i[2*l] + in_i[2*l + 1];
+      assign cnt_l1[l] = {1'b0, in_i[2*l]} + {1'b0, in_i[2*l + 1]};
     end
   endgenerate
 
   generate for(m = 0; m < 8; m++)
     begin
-      assign cnt_l2[m] = cnt_l1[2*m] + cnt_l1[2*m + 1];
+      assign cnt_l2[m] = {1'b0, cnt_l1[2*m]} + {1'b0, cnt_l1[2*m + 1]};
     end
   endgenerate
 
   generate for(n = 0; n < 4; n++)
     begin
-      assign cnt_l3[n] = cnt_l2[2*n] + cnt_l2[2*n + 1];
+      assign cnt_l3[n] = {1'b0, cnt_l2[2*n]} + {1'b0, cnt_l2[2*n + 1]};
     end
   endgenerate
 
   generate for(p = 0; p < 2; p++)
     begin
-      assign cnt_l4[p] = cnt_l3[2*p] + cnt_l3[2*p + 1];
+      assign cnt_l4[p] = {1'b0, cnt_l3[2*p]} + {1'b0, cnt_l3[2*p + 1]};
     end
   endgenerate
 
-  assign result_o = cnt_l4[0] + cnt_l4[1];
+  assign result_o = {1'b0, cnt_l4[0]} + {1'b0, cnt_l4[1]};
 
 endmodule

id_stage.sv

@@ -431,7 +431,7 @@ module riscv_id_stage
   ///////////////////////////////////////////////
 
   // hwloop register id
-  assign hwloop_regid_int = instr[8:7];   // rd contains hwloop register id
+  assign hwloop_regid_int = instr[7];   // rd contains hwloop register id
 
   // hwloop target mux
   always_comb

mult.sv

@@ -59,7 +59,7 @@ module riscv_mult
 
   logic [16:0] short_op_a;
   logic [16:0] short_op_b;
-  logic [31:0] short_mac;
+  logic [33:0] short_mac;
   logic [31:0] short_round, short_round_tmp;
   logic [31:0] short_result;
 
@@ -108,7 +108,7 @@ module riscv_mult
 
   logic [1:0][16:0] dot_short_op_a;
   logic [1:0][16:0] dot_short_op_b;
-  logic [1:0][31:0] dot_short_mul;
+  logic [1:0][33:0] dot_short_mul;
   logic [31:0]      dot_short_result;
 
 
@@ -127,7 +127,9 @@ module riscv_mult
   assign dot_char_mul[2]  = $signed(dot_char_op_a[2]) * $signed(dot_char_op_b[2]);
   assign dot_char_mul[3]  = $signed(dot_char_op_a[3]) * $signed(dot_char_op_b[3]);
 
-  assign dot_char_result  = $signed(dot_char_mul[0]) + $signed(dot_char_mul[1]) + $signed(dot_char_mul[2]) + $signed(dot_char_mul[3]) + $signed(dot_op_c_i);
+  assign dot_char_result  = $signed(dot_char_mul[0]) + $signed(dot_char_mul[1]) +
+                            $signed(dot_char_mul[2]) + $signed(dot_char_mul[3]) +
+                            $signed(dot_op_c_i);
 
 
   assign dot_short_op_a[0] = {dot_signed_i[1] & dot_op_a_i[15], dot_op_a_i[15: 0]};
@@ -139,7 +141,7 @@ module riscv_mult
   assign dot_short_mul[0]  = $signed(dot_short_op_a[0]) * $signed(dot_short_op_b[0]);
   assign dot_short_mul[1]  = $signed(dot_short_op_a[1]) * $signed(dot_short_op_b[1]);
 
-  assign dot_short_result  = $signed(dot_short_mul[0]) + $signed(dot_short_mul[1]) + $signed(dot_op_c_i);
+  assign dot_short_result  = $signed(dot_short_mul[0][31:0]) + $signed(dot_short_mul[1][31:0]) + $signed(dot_op_c_i);
 
 
   ////////////////////////////////////////////////////////

register_file_ff.sv

@@ -65,9 +65,9 @@ module riscv_register_file
   begin : we_a_decoder
     for (int i = 0; i < NUM_WORDS; i++) begin
       if (waddr_a_i == i)
-        we_a_dec[i] <= we_a_i;
+        we_a_dec[i] = we_a_i;
       else
-        we_a_dec[i] <= 1'b0;
+        we_a_dec[i] = 1'b0;
     end
   end
 
@@ -75,9 +75,9 @@ module riscv_register_file
   begin : we_b_decoder
     for (int i=0; i<NUM_WORDS; i++) begin
       if (waddr_b_i == i)
-        we_b_dec[i] <= we_b_i;
+        we_b_dec[i] = we_b_i;
       else
-        we_b_dec[i] <= 1'b0;
+        we_b_dec[i] = 1'b0;
     end
   end
 
@@ -88,18 +88,15 @@ module riscv_register_file
     for (i = 1; i < NUM_WORDS; i++)
     begin : rf_gen
 
-      always_ff @(posedge clk or negedge rst_n)
+      always_ff @(posedge clk, negedge rst_n)
       begin : register_write_behavioral
         if (rst_n==1'b0) begin
           rf_reg[i] <= 'b0;
-        end
-        else begin
+        end else begin
           if(we_b_dec[i] == 1'b1)
             rf_reg[i] <= wdata_b_i;
           else if(we_a_dec[i] == 1'b1)
             rf_reg[i] <= wdata_a_i;
-          else
-            rf_reg[i] <= rf_reg[i];
         end
       end
 
@@ -110,19 +107,8 @@ module riscv_register_file
 
   endgenerate
 
-  always_comb
-  begin : register_read_a_behavioral
-    rdata_a_o <= rf_reg[raddr_a_i];
-  end
-
-  always_comb
-  begin : register_read_b_behavioral
-    rdata_b_o <= rf_reg[raddr_b_i];
-  end
-
-  always_comb
-  begin : register_read_c_behavioral
-    rdata_c_o <= rf_reg[raddr_c_i];
-  end
+  assign rdata_a_o = rf_reg[raddr_a_i];
+  assign rdata_b_o = rf_reg[raddr_b_i];
+  assign rdata_c_o = rf_reg[raddr_c_i];
 
 endmodule