mirror of
https://github.com/openhwgroup/cve2.git
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Add special event load instruction (p.elw)
This commit is contained in:
Andreas Traber
parent
3b127ca326
commit
217adf9dc0
7 changed files with 99 additions and 71 deletions
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@ -141,7 +141,7 @@ module riscv_controller
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// print warning in case of decoding errors
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if (is_decoding_o && illegal_insn_i) begin
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$display("%t: Illegal instruction (core %0d) at PC 0x%h:", $time, riscv_core.core_id_i,
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riscv_id_stage.current_pc_id_i);
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riscv_id_stage.pc_id_i);
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end
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end
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// synopsys translate_on
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@ -58,6 +58,8 @@ module riscv_cs_registers
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output logic [31:0] mepc_o,
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input logic [31:0] curr_pc_id_i,
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input logic [31:0] data_pc_ex_i,
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input logic data_load_event_ex_i,
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input logic exc_save_i,
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input logic exc_restore_i,
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@ -204,7 +206,7 @@ module riscv_cs_registers
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// exception controller gets priority over other writes
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if (exc_save_i) begin
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mepc_n = curr_pc_id_i;
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mepc_n = data_load_event_ex_i ? data_pc_ex_i : curr_pc_id_i; // save EX PC if special event load
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mestatus_n = mstatus_q;
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mstatus_n = 1'b0;
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end
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14
decoder.sv
14
decoder.sv
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@ -81,6 +81,7 @@ module riscv_decoder
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output logic [1:0] data_type_o, // data type on data memory: byte, half word or word
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output logic data_sign_extension_o, // sign extension on read data from data memory
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output logic [1:0] data_reg_offset_o, // offset in byte inside register for stores
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output logic data_load_event_o, // data request is in the special event range
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// hwloop signals
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output logic [2:0] hwloop_we_o, // write enable for hwloop regs
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@ -159,6 +160,7 @@ module riscv_decoder
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data_sign_extension_o = 1'b0;
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data_reg_offset_o = 2'b00;
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data_req = 1'b0;
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data_load_event_o = 1'b0;
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illegal_insn_o = 1'b0;
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trap_insn = 1'b0;
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@ -345,12 +347,12 @@ module riscv_decoder
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endcase
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end
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if (instr_rdata_i[14:12] == 3'b011 || instr_rdata_i[14:12] == 3'b110)
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begin
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// LD, LWU -> RV64 only
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data_req = 1'b0;
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regfile_mem_we = 1'b0;
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regfile_alu_we = 1'b0;
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// special p.elw (event load)
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if (instr_rdata_i[14:12] == 3'b110)
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data_load_event_o = 1'b1;
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if (instr_rdata_i[14:12] == 3'b011) begin
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// LD -> RV64 only
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illegal_insn_o = 1'b1;
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end
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end
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35
id_stage.sv
35
id_stage.sv
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@ -66,8 +66,8 @@ module riscv_id_stage
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input logic illegal_c_insn_i,
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input logic is_compressed_i,
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input logic [31:0] current_pc_if_i,
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input logic [31:0] current_pc_id_i,
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input logic [31:0] pc_if_i,
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input logic [31:0] pc_id_i,
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// Stalls
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output logic halt_if_o, // controller requests a halt of the IF stage
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@ -132,6 +132,9 @@ module riscv_id_stage
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output logic [1:0] data_type_ex_o,
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output logic data_sign_ext_ex_o,
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output logic [1:0] data_reg_offset_ex_o,
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output logic [31:0] data_pc_ex_o,
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output logic data_load_event_ex_o,
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output logic data_misaligned_ex_o,
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output logic prepost_useincr_ex_o,
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@ -269,6 +272,7 @@ module riscv_id_stage
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logic data_sign_ext_id;
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logic [1:0] data_reg_offset_id;
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logic data_req_id;
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logic data_load_event_id;
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// hwloop signals
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logic [N_HWLP_BITS-1:0] hwloop_regid, hwloop_regid_int;
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@ -405,8 +409,8 @@ module riscv_id_stage
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always_comb
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begin
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unique case (hwloop_target_mux_sel)
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1'b0: hwloop_target = current_pc_id_i + {imm_iz_type[30:0], 1'b0};
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1'b1: hwloop_target = current_pc_id_i + {imm_z_type[30:0], 1'b0};
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1'b0: hwloop_target = pc_id_i + {imm_iz_type[30:0], 1'b0};
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1'b1: hwloop_target = pc_id_i + {imm_z_type[30:0], 1'b0};
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endcase
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end
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@ -415,7 +419,7 @@ module riscv_id_stage
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begin
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unique case (hwloop_start_mux_sel)
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1'b0: hwloop_start_int = hwloop_target; // for PC + I imm
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1'b1: hwloop_start_int = current_pc_if_i; // for next PC
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1'b1: hwloop_start_int = pc_if_i; // for next PC
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endcase
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end
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@ -449,8 +453,8 @@ module riscv_id_stage
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always_comb
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begin : jump_target_mux
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unique case (jump_target_mux_sel)
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`JT_JAL: jump_target = current_pc_id_i + imm_uj_type;
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`JT_COND: jump_target = current_pc_id_i + imm_sb_type;
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`JT_JAL: jump_target = pc_id_i + imm_uj_type;
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`JT_COND: jump_target = pc_id_i + imm_sb_type;
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// JALR: Cannot forward RS1, since the path is too long
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`JT_JALR: jump_target = regfile_data_ra_id + imm_i_type;
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@ -475,7 +479,7 @@ module riscv_id_stage
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begin : alu_operand_a_mux
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case (alu_op_a_mux_sel)
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`OP_A_REGA_OR_FWD: alu_operand_a = operand_a_fw_id;
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`OP_A_CURRPC: alu_operand_a = current_pc_id_i;
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`OP_A_CURRPC: alu_operand_a = pc_id_i;
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`OP_A_ZIMM: alu_operand_a = imm_z_type;
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`OP_A_ZERO: alu_operand_a = 32'b0;
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default: alu_operand_a = operand_a_fw_id;
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@ -703,6 +707,7 @@ module riscv_id_stage
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.data_type_o ( data_type_id ),
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.data_sign_extension_o ( data_sign_ext_id ),
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.data_reg_offset_o ( data_reg_offset_id ),
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.data_load_event_o ( data_load_event_id ),
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// hwloop signals
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.hwloop_we_o ( hwloop_we_int ),
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@ -925,7 +930,7 @@ module riscv_id_stage
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end
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else begin
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if (jump_in_id == `BRANCH_COND && id_valid_o)
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branch_pc_ex_o <= current_pc_id_i;
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branch_pc_ex_o <= pc_id_i;
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end
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end
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@ -966,6 +971,8 @@ module riscv_id_stage
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data_sign_ext_ex_o <= 1'b0;
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data_reg_offset_ex_o <= 2'b0;
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data_req_ex_o <= 1'b0;
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data_pc_ex_o <= '0;
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data_load_event_ex_o <= 1'b0;
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data_misaligned_ex_o <= 1'b0;
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@ -1043,6 +1050,15 @@ module riscv_id_stage
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data_type_ex_o <= data_type_id;
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data_sign_ext_ex_o <= data_sign_ext_id;
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data_reg_offset_ex_o <= data_reg_offset_id;
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if (data_load_event_id) begin
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data_pc_ex_o <= pc_id_i;
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data_load_event_ex_o <= 1'b1;
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end else begin
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data_load_event_ex_o <= 1'b0;
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end
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end else begin
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data_load_event_ex_o <= 1'b0;
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end
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data_misaligned_ex_o <= 1'b0;
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@ -1059,6 +1075,7 @@ module riscv_id_stage
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csr_op_ex_o <= `CSR_OP_NONE;
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data_req_ex_o <= 1'b0;
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data_load_event_ex_o <= 1'b0;
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data_misaligned_ex_o <= 1'b0;
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10
if_stage.sv
10
if_stage.sv
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@ -57,8 +57,8 @@ module riscv_if_stage
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output logic [31:0] instr_rdata_id_o, // read instruction is sampled and sent to ID stage for decoding
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output logic is_compressed_id_o, // compressed decoder thinks this is a compressed instruction
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output logic illegal_c_insn_id_o, // compressed decoder thinks this is an invalid instruction
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output logic [31:0] current_pc_if_o,
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output logic [31:0] current_pc_id_o,
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output logic [31:0] pc_if_o,
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output logic [31:0] pc_id_o,
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// Forwarding ports - control signals
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input logic clear_instr_valid_i, // clear instruction valid bit in IF/ID pipe
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@ -304,7 +304,7 @@ module riscv_if_stage
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);
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assign current_pc_if_o = fetch_addr;
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assign pc_if_o = fetch_addr;
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assign if_busy_o = prefetch_busy;
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@ -351,7 +351,7 @@ module riscv_if_stage
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instr_rdata_id_o <= '0;
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illegal_c_insn_id_o <= 1'b0;
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is_compressed_id_o <= 1'b0;
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current_pc_id_o <= '0;
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pc_id_o <= '0;
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is_hwlp_id_q <= 1'b0;
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hwlp_dec_cnt_id_o <= '0;
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end
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@ -364,7 +364,7 @@ module riscv_if_stage
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instr_rdata_id_o <= instr_decompressed;
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illegal_c_insn_id_o <= illegal_c_insn;
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is_compressed_id_o <= instr_compressed_int;
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current_pc_id_o <= current_pc_if_o;
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pc_id_o <= pc_if_o;
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is_hwlp_id_q <= fetch_is_hwlp;
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if (fetch_is_hwlp)
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@ -29,7 +29,7 @@
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// no traces for synthesis, they are not synthesizable
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`ifndef SYNTHESIS
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`define TRACE_EXECUTION
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//`define SIMCHECKER
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`define SIMCHECKER
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`endif
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103
riscv_core.sv
103
riscv_core.sv
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@ -93,8 +93,8 @@ module riscv_core
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logic [31:0] instr_rdata_id; // Instruction sampled inside IF stage
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logic is_compressed_id;
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logic illegal_c_insn_id; // Illegal compressed instruction sent to ID stage
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logic [31:0] current_pc_if; // Current Program counter
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logic [31:0] current_pc_id; // Current Program counter
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logic [31:0] pc_if; // Program counter in IF stage
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logic [31:0] pc_id; // Program counter in ID stage
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logic clear_instr_valid;
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logic pc_set;
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@ -173,6 +173,8 @@ module riscv_core
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logic data_sign_ext_ex;
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logic [1:0] data_reg_offset_ex;
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logic data_req_ex;
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logic [31:0] data_pc_ex;
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logic data_load_event_ex;
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logic data_misaligned_ex;
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// stall control
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@ -279,8 +281,8 @@ module riscv_core
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.instr_rdata_id_o ( instr_rdata_id ),
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.is_compressed_id_o ( is_compressed_id ),
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.illegal_c_insn_id_o ( illegal_c_insn_id ),
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.current_pc_if_o ( current_pc_if ),
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.current_pc_id_o ( current_pc_id ),
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.pc_if_o ( pc_if ),
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.pc_id_o ( pc_id ),
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// control signals
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.clear_instr_valid_i ( clear_instr_valid ),
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@ -360,8 +362,8 @@ module riscv_core
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.illegal_c_insn_i ( illegal_c_insn_id ),
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.is_compressed_i ( is_compressed_id ),
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.current_pc_if_i ( current_pc_if ),
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.current_pc_id_i ( current_pc_id ),
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.pc_if_i ( pc_if ),
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.pc_id_i ( pc_id ),
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// Stalls
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.halt_if_o ( halt_if ),
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@ -418,12 +420,15 @@ module riscv_core
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.csr_hwlp_data_i ( csr_hwlp_data ),
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// LSU
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.data_req_ex_o ( data_req_ex ), // to load store unit
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.data_we_ex_o ( data_we_ex ), // to load store unit
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.data_type_ex_o ( data_type_ex ), // to load store unit
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.data_sign_ext_ex_o ( data_sign_ext_ex ), // to load store unit
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.data_reg_offset_ex_o ( data_reg_offset_ex ), // to load store unit
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.data_misaligned_ex_o ( data_misaligned_ex ), // to load store unit
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.data_req_ex_o ( data_req_ex ), // to load store unit
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.data_we_ex_o ( data_we_ex ), // to load store unit
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.data_type_ex_o ( data_type_ex ), // to load store unit
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.data_sign_ext_ex_o ( data_sign_ext_ex ), // to load store unit
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.data_reg_offset_ex_o ( data_reg_offset_ex ), // to load store unit
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.data_pc_ex_o ( data_pc_ex ), // to load store unit
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.data_load_event_ex_o ( data_load_event_ex ), // to load store unit
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.data_misaligned_ex_o ( data_misaligned_ex ), // to load store unit
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.prepost_useincr_ex_o ( useincr_addr_ex ),
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.data_misaligned_i ( data_misaligned ),
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@ -607,52 +612,54 @@ module riscv_core
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)
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cs_registers_i
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.clk ( clk ),
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.rst_n ( rst_n ),
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// Core and Cluster ID from outside
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.core_id_i ( core_id_i ),
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.cluster_id_i ( cluster_id_i ),
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.core_id_i ( core_id_i ),
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.cluster_id_i ( cluster_id_i ),
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// Interface to CSRs (SRAM like)
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.csr_access_i ( csr_access_ex ),
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.csr_addr_i ( csr_addr ),
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.csr_wdata_i ( csr_wdata ),
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.csr_op_i ( csr_op ),
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.csr_rdata_o ( csr_rdata ),
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.csr_access_i ( csr_access_ex ),
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.csr_addr_i ( csr_addr ),
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.csr_wdata_i ( csr_wdata ),
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.csr_op_i ( csr_op ),
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.csr_rdata_o ( csr_rdata ),
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// Interrupt related control signals
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.irq_enable_o ( irq_enable ),
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.mepc_o ( mepc ),
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.irq_enable_o ( irq_enable ),
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.mepc_o ( mepc ),
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.curr_pc_id_i ( current_pc_id ), // from IF stage
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.exc_save_i ( exc_save_id ),
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.exc_restore_i ( exc_restore_id ),
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.curr_pc_id_i ( pc_id ), // from IF stage
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.data_pc_ex_i ( data_pc_ex ), // from ID/EX pipeline
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.data_load_event_ex_i ( data_load_event_ex ), // from ID/EX pipeline
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.exc_save_i ( exc_save_id ),
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.exc_restore_i ( exc_restore_id ),
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.exc_cause_i ( exc_cause ),
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.save_exc_cause_i ( save_exc_cause ),
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.exc_cause_i ( exc_cause ),
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.save_exc_cause_i ( save_exc_cause ),
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// from hwloop registers
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.hwlp_start_i ( hwlp_start ),
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.hwlp_end_i ( hwlp_end ),
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.hwlp_cnt_i ( hwlp_cnt ),
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.hwlp_start_i ( hwlp_start ),
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.hwlp_end_i ( hwlp_end ),
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.hwlp_cnt_i ( hwlp_cnt ),
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.hwlp_regid_o ( csr_hwlp_regid ),
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.hwlp_we_o ( csr_hwlp_we ),
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.hwlp_data_o ( csr_hwlp_data ),
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.hwlp_regid_o ( csr_hwlp_regid ),
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.hwlp_we_o ( csr_hwlp_we ),
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.hwlp_data_o ( csr_hwlp_data ),
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// performance counter related signals
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.id_valid_i ( id_valid ),
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.is_compressed_i ( is_compressed_id ),
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.is_decoding_i ( is_decoding ),
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.id_valid_i ( id_valid ),
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.is_compressed_i ( is_compressed_id ),
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.is_decoding_i ( is_decoding ),
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.imiss_i ( perf_imiss ),
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.pc_set_i ( pc_set ),
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.jump_i ( perf_jump ),
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.branch_i ( branch_in_ex ),
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.branch_taken_i ( branch_decision ),
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.ld_stall_i ( perf_ld_stall ),
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.jr_stall_i ( perf_jr_stall ),
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.imiss_i ( perf_imiss ),
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.pc_set_i ( pc_set ),
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.jump_i ( perf_jump ),
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.branch_i ( branch_in_ex ),
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.branch_taken_i ( branch_decision ),
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.ld_stall_i ( perf_ld_stall ),
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.jr_stall_i ( perf_jr_stall ),
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.mem_load_i ( data_req_o & data_gnt_i & (~data_we_o) ),
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.mem_store_i ( data_req_o & data_gnt_i & data_we_o ),
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|
|
@ -713,8 +720,8 @@ module riscv_core
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.regfile_rdata_i ( dbg_rdata ),
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|
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// signals for PPC and NPC
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.curr_pc_if_i ( current_pc_if ), // from IF stage
|
||||
.curr_pc_id_i ( current_pc_id ), // from IF stage
|
||||
.curr_pc_if_i ( pc_if ), // from IF stage
|
||||
.curr_pc_id_i ( pc_id ), // from IF stage
|
||||
.branch_pc_i ( branch_pc_ex ), // PC of last executed branch (in EX stage)
|
||||
|
||||
.branch_in_ex_i ( branch_in_ex ),
|
||||
|
|
@ -735,7 +742,7 @@ module riscv_core
|
|||
.core_id ( core_id_i ),
|
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.cluster_id ( cluster_id_i ),
|
||||
|
||||
.pc ( id_stage_i.current_pc_id_i ),
|
||||
.pc ( id_stage_i.pc_id_i ),
|
||||
.instr ( id_stage_i.instr ),
|
||||
.compressed ( id_stage_i.is_compressed_i ),
|
||||
.id_valid ( id_stage_i.id_valid_o ),
|
||||
|
|
@ -794,7 +801,7 @@ module riscv_core
|
|||
.pc_set ( pc_set ),
|
||||
.if_valid ( if_valid ),
|
||||
|
||||
.pc ( id_stage_i.current_pc_id_i ),
|
||||
.pc ( id_stage_i.pc_id_i ),
|
||||
.instr ( id_stage_i.instr ),
|
||||
.is_compressed ( is_compressed_id ),
|
||||
.id_valid ( id_stage_i.id_valid_o ),
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue