github-mirrors/cve2
1
0
Fork 0
mirror of https://github.com/openhwgroup/cve2.git synced 2025-04-22 04:57:25 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

More cleanup, remove unused signal

Browse source
This commit is contained in:
Sven Stucki 2015-09-05 16:33:51 +02:00
parent f9d0911329
commit 24f0a588f5
2 changed files with 0 additions and 11 deletions
Download patch file Download diff file Expand all files Collapse all files

5
ex_stage.sv
View file

@ -62,8 +62,6 @@ module ex_stage
input logic regfile_we_i,
input logic [4:0] regfile_waddr_i,
input logic [31:0] regfile_rb_data_i,
// CSR access
input logic csr_access_i,
input logic [31:0] csr_rdata_i,
@ -71,7 +69,6 @@ module ex_stage
// Output of EX stage pipeline
output logic [4:0] regfile_waddr_wb_o,
output logic regfile_we_wb_o,
output logic [31:0] regfile_rb_data_wb_o,
// Forwarding ports : to ID stage
output logic [4:0] regfile_alu_waddr_fw_o,
@ -165,7 +162,6 @@ module ex_stage
begin
regfile_waddr_wb_o <= 5'b0_0000;
regfile_we_wb_o <= 1'b0;
regfile_rb_data_wb_o <= 32'h0000_0000;
end
else
begin
@ -173,7 +169,6 @@ module ex_stage
begin
regfile_we_wb_o <= regfile_we_i;
regfile_waddr_wb_o <= regfile_waddr_i;
regfile_rb_data_wb_o <= regfile_rb_data_i;
end
end
end

6
riscv_core.sv
View file

@ -116,7 +116,6 @@ module riscv_core
// Register Data
logic [31:0] regfile_rb_data_ex; // from id stage to load/store unit and ex stage
logic [31:0] regfile_rb_data_wb; // from ex stage to sp register
// ALU Control
@ -165,7 +164,6 @@ module riscv_core
logic data_sign_ext_ex;
logic [1:0] data_reg_offset_ex;
logic data_req_ex;
logic [31:0] data_addr_ex;
logic data_misaligned_ex;
logic data_ack_int;
@ -438,13 +436,9 @@ module riscv_core
.regfile_alu_we_i ( regfile_alu_we_ex ),
.regfile_alu_waddr_i ( regfile_alu_waddr_ex ),
//From ID stage.Controller
.regfile_rb_data_i ( regfile_rb_data_ex ),
// Output of ex stage pipeline
.regfile_waddr_wb_o ( regfile_waddr_fw_wb_o ),
.regfile_we_wb_o ( regfile_we_wb ),
.regfile_rb_data_wb_o ( regfile_rb_data_wb ),
// To IF: Jump and branch target and decision
.jump_target_o ( jump_target_ex ),