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Fix

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This commit is contained in:
Markus Wegmann 2017-01-08 10:58:51 +01:00
parent 4f71899e93
commit 25273056f0
3 changed files with 27 additions and 6 deletions
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3
controller.sv
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@ -931,10 +931,13 @@ module riscv_controller
// Assertions // Assertions
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
// CONFIG_REGION: MERGE_ID_EX
`ifdef MERGE_ID_EX
// make sure that taken branches do not happen back-to-back, as this is not // make sure that taken branches do not happen back-to-back, as this is not
// possible without branch prediction in the IF stage // possible without branch prediction in the IF stage
assert property ( assert property (
@(posedge clk) (branch_taken_ex_i) |=> (~branch_taken_ex_i) ) else $warning("Two branches back-to-back are taken"); @(posedge clk) (branch_taken_ex_i) |=> (~branch_taken_ex_i) ) else $warning("Two branches back-to-back are taken");
`endif // MERGE_ID_EX
assert property ( assert property (
@(posedge clk) (~(dbg_req_i & ext_req_i)) ) else $warning("Both dbg_req_i and ext_req_i are active"); @(posedge clk) (~(dbg_req_i & ext_req_i)) ) else $warning("Both dbg_req_i and ext_req_i are active");

14
load_store_unit.sv
View file

@ -93,6 +93,10 @@ module riscv_load_store_unit
`endif `endif
input logic ex_valid_i, input logic ex_valid_i,
// CONFIG_REGION: MERGE_ID_EX
`ifdef MERGE_ID_EX
input logic id_wait_i,
`endif
output logic busy_o output logic busy_o
); );
@ -451,8 +455,13 @@ module riscv_load_store_unit
`ifdef SPLITTED_ADDER `ifdef SPLITTED_ADDER
if (data_req_ex_i & alu_ready_i) begin if (data_req_ex_i & alu_ready_i) begin
`else `else
// CONFIG_REGION: MERGE_ID_EX
`ifdef MERGE_ID_EX
if (data_req_ex_i & ~id_wait_i) begin
`else
if (data_req_ex_i) begin if (data_req_ex_i) begin
`endif `endif
`endif
data_req_o = data_req_ex_i; data_req_o = data_req_ex_i;
lsu_ready_ex_o = 1'b0; lsu_ready_ex_o = 1'b0;
@ -481,7 +490,12 @@ module riscv_load_store_unit
`ifdef SPLITTED_ADDER `ifdef SPLITTED_ADDER
if (data_req_ex_i & alu_ready_i) begin if (data_req_ex_i & alu_ready_i) begin
`else `else
// CONFIG_REGION: MERGE_ID_EX
`ifdef MERGE_ID_EX
if (data_req_ex_i & ~id_wait_i) begin
`else
if (data_req_ex_i) begin if (data_req_ex_i) begin
`endif
`endif `endif
data_req_o = data_req_ex_i; data_req_o = data_req_ex_i;
lsu_ready_ex_o = 1'b0; lsu_ready_ex_o = 1'b0;

4
riscv_core.sv
View file

@ -864,6 +864,10 @@ module riscv_core
`endif `endif
.ex_valid_i ( ex_valid ), .ex_valid_i ( ex_valid ),
// CONFIG_REGION: MERGE_ID_EX
`ifdef MERGE_ID_EX
.id_wait_i ( id_wait ),
`endif
.busy_o ( lsu_busy ) .busy_o ( lsu_busy )
); );