debug mode related TB updates (#160)

dv/uvm/Makefile

@@ -21,7 +21,6 @@ COV_CMP_OPTS := -cm line+tgl+assert+fsm+branch \
                 -cm_tgl structarr \
                 -cm_report noinitial \
                 -cm_seqnoconst \
-                -cm_glitch 0 \
                 -cm_dir ${OUT}/rtl_sim/test.vdb \
                 -cm_hier cover.cfg
 

dv/uvm/riscv_dv_extension/ibex_asm_program_gen.sv

@@ -28,8 +28,15 @@ class ibex_asm_program_gen extends riscv_asm_program_gen;
     instr_stream.push_back(".endm");
     instr_stream.push_back(".section .text.init");
     instr_stream.push_back(".globl _start");
-    // 0x0 is reserved for trap handling
+    // 0x0 - 0xFF is reserved for trap/interrupt handling
+    instr_stream.push_back(".option norvc");
     instr_stream.push_back("j mtvec_handler");
+    // 0x40 debug mode entry
+    instr_stream.push_back(".align 6");
+    instr_stream.push_back("j debug_rom");
+    // 0x44 debug mode exception handler
+    instr_stream.push_back("j debug_exception");
+    instr_stream.push_back(".option rvc");
     // Align the start section to 0x80
     instr_stream.push_back(".align 7");
     instr_stream.push_back("_start: j _reset_entry");

dv/uvm/riscv_dv_extension/ibex_core_setting.sv

@@ -34,6 +34,9 @@ riscv_instr_name_t unsupported_instr[] = {FENCEI};
 // ISA supported by the processor
 riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV32C};
 
+// Debug mode support
+bit support_debug_mode = 1;
+
 // Support delegate trap to user mode
 bit support_umode_trap = 0;
 

dv/uvm/sim

@@ -68,6 +68,7 @@ fi
 
 OUT="$RUN_DIR/rtl_sim"
 CWD=`pwd`
+OPTS=""
 
 # Run each test
 while read asm_test; do
@@ -88,9 +89,15 @@ while read asm_test; do
               -assert nopostproc \
               -cm_name test_${SEED}"
   fi
+  if [[ $BINFILE =~ ebreak ]]; then
+    OPTS="+enable_debug_seq=1"
+  fi
+  if [[ $BINFILE =~ wfi ]]; then
+    OPTS="+enable_irq_seq=1"
+  fi
   CMD="$OUT/vcs_simv +UVM_TESTNAME=core_ibex_base_test \
        ${WAVES_OPTS} +ntb_random_seed=${SEED} +vcs+lic+wait ${COV_OPTS}\
-       +UVM_MAX_QUIT_COUNT=5 +bin=$BINFILE -l sim.log"
+       +UVM_MAX_QUIT_COUNT=5 +bin=$BINFILE -l sim.log ${OPTS}"
   echo "Running simulation for : $CMD"
   $CMD
 done <"$RUN_DIR/asm_test_list"

dv/uvm/tb/core_ibex_tb_top.sv

@@ -9,18 +9,21 @@ module core_ibex_tb_top;
   logic clk;
   logic rst_n;
   logic fetch_enable;
+  logic debug_req;
 
   clk_if ibex_clk_if(.clk(clk));
 
   // TODO(taliu) Resolve the tied-off ports
-  ibex_core_tracer dut(
+  ibex_core_tracer #(.DmHaltAddr(`BOOT_ADDR + 'h40),
+                     .DmExceptionAddr(`BOOT_ADDR + 'h44)
+  ) dut (
     .clk_i(clk),
     .rst_ni(rst_n),
     .test_en_i(1'b1),
     .core_id_i('0),
     .cluster_id_i('0),
     .boot_addr_i(`BOOT_ADDR), // align with spike boot address
-    .debug_req_i('0),
+    .debug_req_i(debug_req),
     .fetch_enable_i(fetch_enable)
   );
 
@@ -65,7 +68,7 @@ module core_ibex_tb_top;
   core_ibex_dut_probe_if dut_if(.clk(clk));
   assign dut_if.ecall = dut.u_ibex_core.id_stage_i.ecall_insn_dec;
   assign fetch_enable = dut_if.fetch_enable;
-  assign dut_if.debug_req = dut.debug_req_i;
+  assign debug_req = dut_if.debug_req;
 
   initial begin
     uvm_config_db#(virtual clk_if)::set(null, "*", "clk_if", ibex_clk_if);

dv/uvm/tests/core_ibex_seq_lib.sv

@@ -30,8 +30,8 @@ class core_base_seq #(type REQ = uvm_sequence_item) extends uvm_sequence#(REQ);
   }
 
   virtual task body();
-    if(!uvm_config_db#(virtual clk_if)::get(null, "", "vif", clk_vif)) begin
-       `uvm_error(get_full_name(), "Cannot get clk_if")
+    if(!uvm_config_db#(virtual clk_if)::get(null, "", "clk_if", clk_vif)) begin
+       `uvm_fatal(get_full_name(), "Cannot get clk_if")
     end
     void'(randomize(delay));
     clk_vif.wait_clks(delay);
@@ -46,7 +46,7 @@ class core_base_seq #(type REQ = uvm_sequence_item) extends uvm_sequence#(REQ);
       end
     end
     seq_finished = 1'b1;
-    `uvm_info(get_full_name(), "Exiting IRQ sequence", UVM_LOW)
+    `uvm_info(get_full_name(), "Exiting sequence", UVM_LOW)
   endtask
 
   virtual task send_req();
@@ -89,12 +89,14 @@ class debug_seq extends core_base_seq;
     if (!uvm_config_db#(virtual core_ibex_dut_probe_if)::get(null, "", "dut_if", dut_vif)) begin
       `uvm_fatal(get_full_name(), "Cannot get dut_if")
     end
+    dut_vif.debug_req <= 1'b0;
     super.body();
   endtask
 
   virtual task send_req();
+    `uvm_info(get_full_name(), "Sending debug request", UVM_HIGH)
     dut_vif.debug_req <= 1'b1;
-    clk_vif.wait_clks(1);
+    clk_vif.wait_clks($urandom_range(1, 20));
     dut_vif.debug_req <= 1'b0;
   endtask