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[ibex/ml] Update the ML testlist

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Signed-off-by: Udi <udij@google.com>
This commit is contained in:
Udi 2020-08-10 12:44:26 -07:00 • committed by udinator
parent 5f899ecb19
commit 3706f5364c
1 changed files with 19 additions and 10 deletions
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29
dv/uvm/core_ibex/riscv_dv_extension/ml_testlist.yaml
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@ -59,6 +59,7 @@
gen_opts: >
+instr_cnt=10000
+num_of_sub_program=5
+enable_write_pmp_csr=1
+illegal_instr_ratio=5
+hint_instr_ratio=5
+no_ebreak=0
@ -78,6 +79,8 @@
+enable_unaligned_load_store=1
+disable_compressed_instr=0
+randomize_csr=0
+enable_b_extension=1
+enable_bitmanip_groups=zbb,zb_tmp,zbt,zbs,zbp,zbf,zbe,zbc,zbr
+boot_mode=u
+stream_name_0=riscv_load_store_rand_instr_stream
+stream_freq_0=4
@ -102,10 +105,12 @@
+stream_name_10=riscv_load_store_stress_instr_stream
+stream_freq_10=4
iterations: 1
no_iss: 1
gcc_opts: >
-mno-strict-align
gen_test: riscv_ml_test
rtl_test: core_ibex_base_test
no_post_compare: 1
# --------------------------------------------------------------------------------
@ -148,6 +153,7 @@
+enable_debug_single_step=1
+instr_cnt=10000
+num_of_sub_program=5
+enable_write_pmp_csr=1
+illegal_instr_ratio=0
+hint_instr_ratio=5
+no_ebreak=1
@ -168,6 +174,8 @@
+enable_unaligned_load_store=1
+disable_compressed_instr=0
+randomize_csr=0
+enable_b_extension=1
+enable_bitmanip_groups=zbb,zb_tmp,zbt,zbs,zbp,zbf,zbe,zbc,zbr
+boot_mode=u
+stream_name_0=riscv_load_store_rand_instr_stream
+stream_freq_0=4
@ -192,6 +200,7 @@
+stream_name_10=riscv_load_store_stress_instr_stream
+stream_freq_10=4
iterations: 1
no_iss: 1
gcc_opts: >
-mno-strict-align
gen_test: riscv_ml_test
@ -200,8 +209,7 @@
+max_interval=100000
+enable_debug_seq=1
rtl_test: core_ibex_debug_intr_basic_test
compare_opts:
compare_final_value_only: 1
no_post_compare: 1
# --------------------------------------------------------------------------------
@ -215,14 +223,12 @@
# parameters relating to simulations with external interrupts.
# --------------------------------------------------------------------------------
# 1) +enable_interrupt and +require_signature_addr must both be 1.
# 2) If using Spike ISS, +enable_timer_irq must be 0, otherwise it can be
# randomized at will.
# 3) As before, +illegal_instr_ratio must be 0, +no_ebreak must be 1,
# 2) As before, +illegal_instr_ratio must be 0, +no_ebreak must be 1,
# and +no_dret must be 1.
# 4) +set_mstatus_tw must be 0.
# 3) One of the RTL simulation options +enable_irq_single_seq or
# 3) +set_mstatus_tw must be 0.
# 4) One of the RTL simulation options +enable_irq_single_seq or
# +enable_irq_multiple_seq must be enabled.
# 4) The RTL simulation option +require_signature_addr must be 1.
# 5) The RTL simulation option +require_signature_addr must be 1.
- test: riscv_rand_irq_test
description: >
@ -232,6 +238,7 @@
+enable_interrupt=1
+enable_timer_irq=1
+instr_cnt=10000
+enable_write_pmp_csr=1
+num_of_sub_program=5
+illegal_instr_ratio=0
+hint_instr_ratio=5
@ -253,6 +260,8 @@
+enable_unaligned_load_store=1
+disable_compressed_instr=0
+randomize_csr=1
+enable_b_extension=1
+enable_bitmanip_groups=zbb,zb_tmp,zbt,zbs,zbp,zbf,zbe,zbc,zbr
+boot_mode=u
+stream_name_0=riscv_load_store_rand_instr_stream
+stream_freq_0=4
@ -277,6 +286,7 @@
+stream_name_10=riscv_load_store_stress_instr_stream
+stream_freq_10=4
iterations: 1
no_iss: 1
gcc_opts: >
-mno-strict-align
gen_test: riscv_ml_test
@ -285,5 +295,4 @@
+enable_irq_single_seq=1
+enable_irq_multiple_seq=0
rtl_test: core_ibex_debug_intr_basic_test
compare_opts:
compare_final_value_only: 1
no_post_compare: 1