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New CSR implementation, fix irq_enable signal
Interrupts can now be switched on and off via CSR write, the current status can be queried by a CSR read. Pending interrupts still TBD.
This commit is contained in:
Sven Stucki
parent
bb693c8e6b
commit
3a4ddb2af3
3 changed files with 113 additions and 93 deletions
155
cs_registers.sv
155
cs_registers.sv
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@ -28,7 +28,7 @@
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module cs_registers
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#(
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parameter N_EXT_PERF_COUNTERS = 0
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)
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)
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(
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// Clock and Reset
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input logic clk,
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@ -38,7 +38,7 @@ module cs_registers
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input logic [4:0] core_id_i,
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input logic [4:0] cluster_id_i,
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// Interface to special purpose registers (SRAM like)
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// Interface to registers (SRAM like)
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input logic [11:0] csr_addr_i,
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input logic [31:0] csr_wdata_i,
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input logic [1:0] csr_op_i,
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@ -48,11 +48,13 @@ module cs_registers
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input logic [31:0] curr_pc_if_i,
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input logic [31:0] curr_pc_id_i,
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input logic save_pc_if_i,
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input logic save_pc_id_i, // TODO: check if both IF/ID pc save is needed
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input logic save_pc_id_i,
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output logic [1:0] irq_enable_o,
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output logic [31:0] epcr_o,
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// Performance Counters
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input logic stall_id_i, // Stall ID stage
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input logic stall_id_i, // stall ID stage
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input logic instr_fetch_i, // instruction fetch
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@ -93,71 +95,94 @@ module cs_registers
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logic is_pcer;
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logic is_pcmr;
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logic is_constant;
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logic is_register;
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logic [31:0] constant_rdata_int;
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logic [31:0] register_rdata_int;
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logic is_readonly;
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logic illegal_address;
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// CSRs and index of CSR to access
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int csr_index; // TODO: check synthesis result
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// Generic CSRs
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int csr_index;
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logic [31:0] csr [0:`CSR_MAX_IDX];
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logic [31:0] csr_n [0:`CSR_MAX_IDX];
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// CSR update logic
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logic [31:0] csr_wdata_int;
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logic csr_we_int;
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// Interrupt control signals
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logic irq_enable, irq_enable_n;
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assign is_readonly = (csr_addr_i[11:10] == 2'b11);
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assign illegal_address = ~is_constant && ~is_register;
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// read logic
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always_comb
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begin
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csr_rdata_int = 'x;
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case (csr_addr_i)
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// mstatus: always M-mode, contains IE bit
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12'h300: csr_rdata_int = {29'b0, 2'b11, irq_enable};
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// mscratch
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12'h340: csr_rdata_int = csr[`CSR_IDX_MSCRATCH];
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// mepc: exception program counter
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12'h341: csr_rdata_int = csr[`CSR_IDX_MEPC];
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// mcpuid: RV32I
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12'hF00: csr_rdata_int = 32'h00_00_01_00;
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// mimpid: PULP, anonymous source (no allocated ID yet)
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12'hF01: csr_rdata_int = 32'h00_00_80_00;
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// mhartid: unique hardware thread id
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12'hF10: csr_rdata_int = {22'b0, cluster_id_i, core_id_i};
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endcase
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end
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// write logic
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always_comb
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begin
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csr_n = csr;
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irq_enable_n = irq_enable;
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case (csr_addr_i)
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// mstatus: always M-mode, contains IE bit
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12'h300: if (csr_we_int) irq_enable_n = csr_wdata_int[0];
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// mscratch
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12'h340: if (csr_we_int) csr_n[`CSR_IDX_MSCRATCH] = csr_wdata_int;
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// mepc: exception program counter
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12'h341: if (csr_we_int) csr_n[`CSR_IDX_MEPC] = csr_wdata_int;
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endcase
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end
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// CSR operation logic
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always_comb
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begin
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csr_wdata_int = csr_wdata_i;
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csr_we_int = 1'b1;
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unique case (csr_op_i)
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`CSR_OP_WRITE: csr_wdata_int = csr_wdata_i;
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`CSR_OP_SET: csr_wdata_int = csr_wdata_i | csr_rdata_o;
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`CSR_OP_CLEAR: csr_wdata_int = csr_wdata_i & ~(csr_rdata_o);
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`CSR_OP_NONE: begin
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csr_wdata_int = csr_wdata_i;
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csr_we_int = 1'b0;
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end
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endcase
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end
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// output mux
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always_comb
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begin
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csr_rdata_o = 'x;
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csr_rdata_o = csr_rdata_int;
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if (is_constant == 1'b1)
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csr_rdata_o = constant_rdata_int;
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else if (is_register == 1'b1)
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csr_rdata_o = register_rdata_int;
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else // must be performance counter
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// performance counters
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if (is_pccr || is_pcer || is_pcmr)
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csr_rdata_o = perf_rdata;
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end
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// address decoder for constant CSRs
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always_comb
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begin
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constant_rdata_int = '0;
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is_constant = 1'b1;
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unique case (csr_addr_i)
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12'hF00: constant_rdata_int = 32'h00_00_01_00; // mcpuid: RV32I
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12'hF01: constant_rdata_int = 32'h00_00_80_00; // mimpid: PULP3, anonymous source (no allocated ID)
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12'hF10: constant_rdata_int = {22'b0, cluster_id_i, core_id_i}; // mhartid: unique hardware thread id
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default: is_constant = 1'b0;
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endcase
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end
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// address decoder for regular CSRs
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always_comb
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begin
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csr_index = '0;
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is_register = 1'b1;
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unique case (csr_addr_i)
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12'h340: csr_index = `CSR_IDX_MSCRATCH;
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12'h341: csr_index = `CSR_IDX_MEPC;
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default: is_register = 1'b0;
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endcase
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end
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assign register_rdata_int = csr[csr_index];
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// directly output some registers
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assign epcr_o = csr[`CSR_IDX_MEPC];
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assign irq_enable_o = irq_enable;
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assign epcr_o = csr[`CSR_IDX_MEPC];
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// actual registers
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@ -165,23 +190,16 @@ module cs_registers
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begin
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if (rst_n == 1'b0)
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begin
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csr <= '{default: 32'b0}; // new SV syntax TODO: check synthesis result
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csr <= '{default: 32'b0};
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irq_enable <= 1'b0;
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end
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else
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begin
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// write CSR through instruction
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if (is_readonly == 1'b0 && is_pccr == 1'b0) begin
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unique case (csr_op_i)
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`CSR_OP_NONE: ;
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`CSR_OP_WRITE: csr[csr_index] <= csr_wdata_i;
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`CSR_OP_SET: csr[csr_index] <= csr_wdata_i | register_rdata_int;
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`CSR_OP_CLEAR: csr[csr_index] <= csr_wdata_i & ~(register_rdata_int);
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endcase
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end
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// update CSRs
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csr <= csr_n;
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irq_enable <= irq_enable_n;
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// writes from exception controller get priority
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// write exception PC
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// exception PC writes from exception controller get priority
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if (save_pc_if_i == 1'b1)
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csr[`CSR_IDX_MEPC] <= curr_pc_if_i;
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else if (save_pc_id_i == 1'b1)
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@ -199,7 +217,6 @@ module cs_registers
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// //
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/////////////////////////////////////////////////////////////////
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assign PCCR_in[0] = 1'b1; // cycle counter
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assign PCCR_in[1] = ~stall_id_i; // instruction counter
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assign PCCR_in[2] = ld_stall_i & (~stall_id_q); // nr of load use hazards
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@ -674,7 +674,7 @@ module id_stage
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.irq_enable_i ( irq_enable_i ),
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.irq_present_o ( irq_present ),
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// SPR
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// CSR
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.save_pc_if_o ( save_pc_if_o ),
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.save_pc_id_o ( save_pc_id_o ),
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.save_sr_o ( save_sr_o ),
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@ -30,7 +30,7 @@
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module riscv_core
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#(
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parameter N_EXT_PERF_COUNTERS = 0
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parameter N_EXT_PERF_COUNTERS = 0
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)
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(
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// Clock and Reset
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@ -110,8 +110,8 @@ module riscv_core
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logic stall_ex; // Stall EX Stage
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logic stall_wb; // Stall write back stage
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logic core_busy;
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logic if_busy;
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logic core_busy;
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logic if_busy;
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// Register Data
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@ -559,34 +559,37 @@ module riscv_core
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)
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cs_registers_i
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.clk ( clk ),
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.rst_n ( rst_n ),
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// Core and Cluster ID from outside
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.core_id_i ( core_id_i ),
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.cluster_id_i ( cluster_id_i ),
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.core_id_i ( core_id_i ),
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.cluster_id_i ( cluster_id_i ),
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// Interface to Special register (SRAM LIKE)
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.csr_addr_i ( csr_addr ),
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.csr_wdata_i ( csr_wdata ),
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.csr_op_i ( csr_op ),
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.csr_rdata_o ( csr_rdata ),
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// Interface to CSRs (SRAM like)
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.csr_addr_i ( csr_addr ),
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.csr_wdata_i ( csr_wdata ),
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.csr_op_i ( csr_op ),
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.csr_rdata_o ( csr_rdata ),
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.curr_pc_if_i ( current_pc_if ), // from IF stage
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.curr_pc_id_i ( current_pc_id ), // from IF stage
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.save_pc_if_i ( save_pc_if ),
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.save_pc_id_i ( save_pc_id ),
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.epcr_o ( epcr ),
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// Control signals for the core
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.curr_pc_if_i ( current_pc_if ), // from IF stage
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.curr_pc_id_i ( current_pc_id ), // from IF stage
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.save_pc_if_i ( save_pc_if ),
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.save_pc_id_i ( save_pc_id ),
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.irq_enable_o ( irq_enable )
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.epcr_o ( epcr ),
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// performance counter related signals
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.stall_id_i ( stall_id ),
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.stall_id_i ( stall_id ),
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.instr_fetch_i ( ~instr_ack_int ),
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.instr_fetch_i ( ~instr_ack_int ),
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.jump_i ( perf_jump ),
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.branch_i ( perf_branch ),
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.ld_stall_i ( perf_ld_stall ),
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.jr_stall_i ( perf_jr_stall ),
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.jump_i ( perf_jump ),
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.branch_i ( perf_branch ),
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.ld_stall_i ( perf_ld_stall ),
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.jr_stall_i ( perf_jr_stall ),
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.mem_load_i ( data_req_o & data_gnt_i & (~data_we_o) ),
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.mem_store_i ( data_req_o & data_gnt_i & data_we_o ),
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