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Merge branch_pc_ex and data_pc_ex, allow debugging during p.elw
This commit is contained in:
Andreas Traber
parent
0b5f992952
commit
3b766501af
5 changed files with 77 additions and 75 deletions
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@ -59,6 +59,7 @@ module riscv_controller
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// LSU
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input logic data_req_ex_i, // data memory access is currently performed in EX stage
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input logic data_misaligned_i,
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input logic data_load_event_i,
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// from ALU
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input logic mult_multicycle_i, // multiplier is taken multiple cycles and uses op c as storage
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@ -328,6 +329,13 @@ module riscv_controller
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ctrl_fsm_ns = DBG_WAIT_BRANCH;
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else
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ctrl_fsm_ns = DBG_SIGNAL;
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end else if (data_load_event_i) begin
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// special case for p.elw
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// If there was a load event (which means p.elw), we go to debug
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// even though we are still blocked
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// we don't have to distuinguish between branch and non-branch,
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// since the p.elw sits in the EX stage
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ctrl_fsm_ns = DBG_SIGNAL;
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end
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end
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end
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@ -57,8 +57,8 @@ module riscv_cs_registers
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output logic irq_enable_o,
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output logic [31:0] mepc_o,
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input logic [31:0] curr_pc_id_i,
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input logic [31:0] data_pc_ex_i,
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input logic [31:0] pc_id_i,
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input logic [31:0] pc_ex_i,
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input logic data_load_event_ex_i,
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input logic exc_save_i,
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input logic exc_restore_i,
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@ -206,7 +206,7 @@ module riscv_cs_registers
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// exception controller gets priority over other writes
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if (exc_save_i) begin
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mepc_n = data_load_event_ex_i ? data_pc_ex_i : curr_pc_id_i; // save EX PC if special event load
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mepc_n = data_load_event_ex_i ? pc_ex_i : pc_id_i; // save EX PC if special event load
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mestatus_n = mstatus_q;
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mstatus_n = 1'b0;
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end
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@ -65,9 +65,11 @@ module riscv_debug_unit
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input logic [31:0] csr_rdata_i,
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// Signals for PPC & NPC register
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input logic [31:0] curr_pc_if_i,
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input logic [31:0] curr_pc_id_i,
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input logic [31:0] branch_pc_i,
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input logic [31:0] pc_if_i,
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input logic [31:0] pc_id_i,
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input logic [31:0] pc_ex_i,
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input logic data_load_event_i,
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input logic branch_in_ex_i,
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input logic branch_taken_i,
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@ -407,24 +409,24 @@ module riscv_debug_unit
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begin
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pc_tracking_fsm_ns = pc_tracking_fsm_cs;
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ppc_int = curr_pc_id_i;
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npc_int = curr_pc_if_i;
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ppc_int = pc_id_i;
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npc_int = pc_if_i;
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// PPC/NPC mux
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unique case (pc_tracking_fsm_cs)
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IFID: begin
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ppc_int = curr_pc_id_i;
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npc_int = curr_pc_if_i;
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ppc_int = pc_id_i;
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npc_int = pc_if_i;
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end
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IFEX: begin
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ppc_int = branch_pc_i;
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npc_int = curr_pc_if_i;
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ppc_int = pc_ex_i;
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npc_int = pc_if_i;
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end
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IDEX: begin
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ppc_int = branch_pc_i;
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npc_int = curr_pc_id_i;
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ppc_int = pc_ex_i;
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npc_int = pc_id_i;
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if (jump_req_o)
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pc_tracking_fsm_ns = IFEX;
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@ -444,6 +446,9 @@ module riscv_debug_unit
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pc_tracking_fsm_ns = IFEX;
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else
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pc_tracking_fsm_ns = IDEX;
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end else if (data_load_event_i) begin
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// for p.elw
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pc_tracking_fsm_ns = IDEX;
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end
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end
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end
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30
id_stage.sv
30
id_stage.sv
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@ -82,7 +82,7 @@ module riscv_id_stage
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input logic wb_valid_i, // WB stage is done
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// Pipeline ID/EX
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output logic [31:0] branch_pc_ex_o,
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output logic [31:0] pc_ex_o,
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output logic [31:0] alu_operand_a_ex_o,
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output logic [31:0] alu_operand_b_ex_o,
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@ -137,7 +137,6 @@ module riscv_id_stage
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output logic [1:0] data_type_ex_o,
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output logic data_sign_ext_ex_o,
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output logic [1:0] data_reg_offset_ex_o,
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output logic [31:0] data_pc_ex_o,
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output logic data_load_event_ex_o,
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output logic data_misaligned_ex_o,
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@ -839,6 +838,7 @@ module riscv_id_stage
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// LSU
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.data_req_ex_i ( data_req_ex_o ),
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.data_misaligned_i ( data_misaligned_i ),
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.data_load_event_i ( data_load_event_ex_o ),
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// ALU
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.mult_multicycle_i ( mult_multicycle_i ),
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@ -998,17 +998,6 @@ module riscv_id_stage
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// |___|____/ |_____/_/\_\ |_| |___|_| |_____|_____|___|_| \_|_____| //
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// //
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/////////////////////////////////////////////////////////////////////////////////
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always_ff @(posedge clk, negedge rst_n)
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begin
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if (rst_n == 1'b0)
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begin
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branch_pc_ex_o <= '0;
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end
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else begin
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if (jump_in_id == `BRANCH_COND && id_valid_o)
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branch_pc_ex_o <= pc_id_i;
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end
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end
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always_ff @(posedge clk, negedge rst_n)
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begin : ID_EX_PIPE_REGISTERS
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@ -1052,11 +1041,12 @@ module riscv_id_stage
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data_sign_ext_ex_o <= 1'b0;
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data_reg_offset_ex_o <= 2'b0;
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data_req_ex_o <= 1'b0;
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data_pc_ex_o <= '0;
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data_load_event_ex_o <= 1'b0;
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data_misaligned_ex_o <= 1'b0;
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pc_ex_o <= '0;
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branch_in_ex_o <= 1'b0;
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end
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@ -1139,19 +1129,17 @@ module riscv_id_stage
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data_type_ex_o <= data_type_id;
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data_sign_ext_ex_o <= data_sign_ext_id;
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data_reg_offset_ex_o <= data_reg_offset_id;
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if (data_load_event_id) begin
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data_pc_ex_o <= pc_id_i;
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data_load_event_ex_o <= 1'b1;
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end else begin
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data_load_event_ex_o <= 1'b0;
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end
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data_load_event_ex_o <= data_load_event_id;;
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end else begin
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data_load_event_ex_o <= 1'b0;
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end
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data_misaligned_ex_o <= 1'b0;
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if ((jump_in_id == `BRANCH_COND) || data_load_event_id) begin
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pc_ex_o <= pc_id_i;
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end
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branch_in_ex_o <= jump_in_id == `BRANCH_COND;
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end else if(ex_ready_i) begin
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// EX stage is ready but we don't have a new instruction for it,
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@ -124,7 +124,7 @@ module riscv_core
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logic lsu_busy;
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logic [31:0] branch_pc_ex; // PC of last executed branch
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logic [31:0] pc_ex; // PC of last executed branch or p.elw
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// ALU Control
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logic [`ALU_OP_WIDTH-1:0] alu_operator_ex;
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@ -425,7 +425,7 @@ module riscv_core
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.wb_valid_i ( wb_valid ),
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// From the Pipeline ID/EX
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.branch_pc_ex_o ( branch_pc_ex ),
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.pc_ex_o ( pc_ex ),
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.alu_operator_ex_o ( alu_operator_ex ),
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.alu_operand_a_ex_o ( alu_operand_a_ex ),
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@ -477,7 +477,6 @@ module riscv_core
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.data_type_ex_o ( data_type_ex ), // to load store unit
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.data_sign_ext_ex_o ( data_sign_ext_ex ), // to load store unit
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.data_reg_offset_ex_o ( data_reg_offset_ex ), // to load store unit
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.data_pc_ex_o ( data_pc_ex ), // to load store unit
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.data_load_event_ex_o ( data_load_event_ex ), // to load store unit
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.data_misaligned_ex_o ( data_misaligned_ex ), // to load store unit
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@ -696,8 +695,8 @@ module riscv_core
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.irq_enable_o ( irq_enable ),
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.mepc_o ( mepc ),
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.curr_pc_id_i ( pc_id ), // from IF stage
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.data_pc_ex_i ( data_pc_ex ), // from ID/EX pipeline
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.pc_id_i ( pc_id ), // from IF stage
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.pc_ex_i ( pc_ex ), // from ID/EX pipeline
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.data_load_event_ex_i ( data_load_event_ex ), // from ID/EX pipeline
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.exc_save_i ( exc_save_id ),
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.exc_restore_i ( exc_restore_id ),
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@ -754,55 +753,57 @@ module riscv_core
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riscv_debug_unit debug_unit_i
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(
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.clk ( clk_i ), // always-running clock for debug
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.rst_n ( rst_ni ),
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.clk ( clk_i ), // always-running clock for debug
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.rst_n ( rst_ni ),
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// Debug Interface
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.debug_req_i ( debug_req_i ),
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.debug_gnt_o ( debug_gnt_o ),
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.debug_rvalid_o ( debug_rvalid_o ),
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.debug_addr_i ( debug_addr_i ),
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.debug_we_i ( debug_we_i ),
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.debug_wdata_i ( debug_wdata_i ),
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.debug_rdata_o ( debug_rdata_o ),
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.debug_halt_i ( debug_halt_i ),
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.debug_halted_o ( debug_halted_o ),
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.debug_req_i ( debug_req_i ),
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.debug_gnt_o ( debug_gnt_o ),
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.debug_rvalid_o ( debug_rvalid_o ),
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.debug_addr_i ( debug_addr_i ),
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.debug_we_i ( debug_we_i ),
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.debug_wdata_i ( debug_wdata_i ),
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.debug_rdata_o ( debug_rdata_o ),
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.debug_halt_i ( debug_halt_i ),
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.debug_halted_o ( debug_halted_o ),
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// To/From Core
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.settings_o ( dbg_settings ),
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.trap_i ( dbg_trap ),
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.exc_cause_i ( exc_cause ),
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.stall_o ( dbg_stall ),
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.dbg_req_o ( dbg_req ),
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.dbg_ack_i ( dbg_ack ),
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.settings_o ( dbg_settings ),
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.trap_i ( dbg_trap ),
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.exc_cause_i ( exc_cause ),
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.stall_o ( dbg_stall ),
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.dbg_req_o ( dbg_req ),
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.dbg_ack_i ( dbg_ack ),
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// register file read port
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.regfile_rreq_o ( dbg_reg_rreq ),
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.regfile_raddr_o ( dbg_reg_raddr ),
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.regfile_rdata_i ( dbg_reg_rdata ),
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.regfile_rreq_o ( dbg_reg_rreq ),
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.regfile_raddr_o ( dbg_reg_raddr ),
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.regfile_rdata_i ( dbg_reg_rdata ),
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// register file write port
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.regfile_wreq_o ( dbg_reg_wreq ),
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.regfile_waddr_o ( dbg_reg_waddr ),
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.regfile_wdata_o ( dbg_reg_wdata ),
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.regfile_wreq_o ( dbg_reg_wreq ),
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.regfile_waddr_o ( dbg_reg_waddr ),
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.regfile_wdata_o ( dbg_reg_wdata ),
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// CSR read/write port
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.csr_req_o ( dbg_csr_req ),
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.csr_addr_o ( dbg_csr_addr ),
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.csr_we_o ( dbg_csr_we ),
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.csr_wdata_o ( dbg_csr_wdata ),
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.csr_rdata_i ( csr_rdata ),
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.csr_req_o ( dbg_csr_req ),
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.csr_addr_o ( dbg_csr_addr ),
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.csr_we_o ( dbg_csr_we ),
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.csr_wdata_o ( dbg_csr_wdata ),
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.csr_rdata_i ( csr_rdata ),
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// signals for PPC and NPC
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.curr_pc_if_i ( pc_if ), // from IF stage
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.curr_pc_id_i ( pc_id ), // from IF stage
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.branch_pc_i ( branch_pc_ex ), // PC of last executed branch (in EX stage)
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.pc_if_i ( pc_if ), // from IF stage
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.pc_id_i ( pc_id ), // from IF stage
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.pc_ex_i ( pc_ex ), // PC of last executed branch (in EX stage) or p.elw
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.branch_in_ex_i ( branch_in_ex ),
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.branch_taken_i ( branch_decision ),
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.data_load_event_i ( data_load_event_ex ),
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.jump_addr_o ( dbg_jump_addr ), // PC from debug unit
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.jump_req_o ( dbg_jump_req ) // set PC to new value
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.branch_in_ex_i ( branch_in_ex ),
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.branch_taken_i ( branch_decision ),
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.jump_addr_o ( dbg_jump_addr ), // PC from debug unit
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.jump_req_o ( dbg_jump_req ) // set PC to new value
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);
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