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[rtl, bitmanip] Clarify situation around zext.[bh] pseudo-instructions

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This is related to lowRISC/Ibex#1228.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
This commit is contained in:
Pirmin Vogel 2021-11-26 16:40:33 +01:00
parent da85ce5ecf
commit 40dab87448
2 changed files with 20 additions and 12 deletions
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17
rtl/ibex_tracer.sv
View file

@ -855,9 +855,12 @@ module ibex_tracer (
INSN_SLTIU: decode_i_insn("sltiu");
INSN_XORI: decode_i_insn("xori");
INSN_ORI: decode_i_insn("ori");
// Version 0.92 of the Bitmanip Extension defines the pseudo-instruction
// zext.b rd rs = andi rd, rs, 255.
// Currently instruction set simulators don't output this pseudo-instruction.
// Unlike the ratified v.1.0.0 bitmanip extension, the v.0.94 draft extension continues to
// define the pseudo-instruction
// zext.b rd rs = andi rd, rs, 255.
// However, for now the tracer doesn't emit this due to a lack of support in the LLVM and
// GCC toolchains. Enabling this functionality when the time is right is tracked in
// https://github.com/lowRISC/ibex/issues/1228
INSN_ANDI: decode_i_insn("andi");
// INSN_ANDI:begin
// casez (rvfi_insn)
@ -922,9 +925,11 @@ module ibex_tracer (
INSN_XNOR: decode_r_insn("xnor");
INSN_ORN: decode_r_insn("orn");
INSN_ANDN: decode_r_insn("andn");
// Version 0.92 of the Bitmanip Extension defines the pseudo-instruction
// zext.h rd rs = pack rd, rs, zero.
// Currently instruction set simulators don't output this pseudo-instruction.
// The ratified v.1.0.0 bitmanip extension defines the pseudo-instruction
// zext.h rd rs = pack rd, rs, zero.
// However, for now the tracer doesn't emit this due to a lack of support in the LLVM and
// GCC toolchains. Enabling this functionality when the time is right is tracked in
// https://github.com/lowRISC/ibex/issues/1228
INSN_PACK: decode_r_insn("pack");
// INSN_PACK: begin
// casez (rvfi_insn)

15
rtl/ibex_tracer_pkg.sv
View file

@ -86,12 +86,15 @@ package ibex_tracer_pkg;
parameter logic [31:0] INSN_CPOP = { 12'b011000000010, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} };
parameter logic [31:0] INSN_SEXTB = { 12'b011000000100, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} };
parameter logic [31:0] INSN_SEXTH = { 12'b011000000101, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} };
// The ZEXT.B and ZEXT.H pseudo-instructions are currently not emitted by the tracer due to a lack
// of support in the LLVM and GCC toolchains. Enabling this functionality when the time is right is
// tracked in https://github.com/lowRISC/ibex/issues/1228
// sext -- pseudoinstruction: andi rd, rs 255
// parameter logic [31:0] INSN_ZEXTB = { 4'b0000, 8'b11111111, 5'h?, 3'b111, 5'h?, {OPCODE_OP_IMM} };
// sext -- pseudoinstruction: pack rd, rs zero
// The zext.h and zext.b pseudo-instructions are defined in the ratified v.1.0.0 and draft v.0.94
// specifications of the bitmanip extension, respectively. They are currently not emitted by the
// tracer due to a lack of support in the LLVM and GCC toolchains. Enabling this functionality
// when the time is right is tracked in https://github.com/lowRISC/ibex/issues/1228
// zext.b -- pseudo-instruction: andi rd, rs 255
// parameter logic [31:0] INSN_ZEXTB =
// { 4'b0000, 8'b11111111, 5'h?, 3'b111, 5'h?, {OPCODE_OP_IMM} };
// zext.h -- pseudo-instruction: pack rd, rs zero
// parameter logic [31:0] INSN_ZEXTH = { 7'b0000100, 5'b00000, 5'h?, 3'b100, 5'h?, {OPCODE_OP} };
parameter logic [31:0] INSN_ROL = { 7'b0110000, 10'h?, 3'b001, 5'h?, {OPCODE_OP} };