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[bitmanip, doc] Update info on bitmanip support and area numbers
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
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Pirmin Vogel
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4 changed files with 46 additions and 42 deletions
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@ -29,8 +29,8 @@ These are configurations on which lowRISC is focusing for performance evaluation
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| ------ | ------- | --------| ----------| -------------------- |
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| Features | RV32EC | RV32IMC, 3 cycle mult | RV32IMC, 1 cycle mult, Branch target ALU, Writeback stage | RV32IMCB, 1 cycle mult, Branch target ALU, Writeback stage, 16 PMP regions |
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| Performance (CoreMark/MHz) | 0.904 | 2.47 | 3.13 | 3.13 |
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| Area - Yosys (kGE) | 17.44 | 26.06 | 35.64 | 58.74 |
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| Area - Commercial (estimated kGE) | ~16 | ~24 | ~33 | ~54 |
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| Area - Yosys (kGE) | 16.85 | 26.60 | 32.48 | 66.02 |
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| Area - Commercial (estimated kGE) | ~15 | ~24 | ~30 | ~61 |
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| Verification status | Red | Green | Amber | Amber |
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Notes:
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@ -46,8 +46,8 @@ Notes:
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Amber indicates that some verification has been performed, but the configuration is still experimental.
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Red indicates a configuration with minimal/no verification.
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Users must make their own assessment of verification readiness for any tapeout.
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* v0.92 of the RISC-V Bit Manipulation Extension is supported.
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This is *not ratified* and there may be changes for the v1.0 ratified version.
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* v.1.0.0 of the RISC-V Bit-Manipulation Extension is supported as well as the remaining sub-extensions of draft v.0.93 of the bitmanip spec.
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The latter are *not ratified* and there may be changes before ratification.
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See [Standards Compliance](https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html) in the Ibex documentation for more information.
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## Documentation
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@ -8,7 +8,7 @@ It follows these specifications:
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* `RISC-V Instruction Set Manual, Volume II: Privileged Architecture, document version 20190608-Base-Ratified (June 8, 2019) <https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMFDQC-and-Priv-v1.11/riscv-privileged-20190608.pdf>`_.
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Ibex implements the Machine ISA version 1.11.
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* `RISC-V External Debug Support, version 0.13.2 <https://content.riscv.org/wp-content/uploads/2019/03/riscv-debug-release.pdf>`_
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* `RISC-V Bit Manipulation Extension, version 0.92 (draft from November 8, 2019) <https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.92.pdf>`_
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* `RISC-V Bit-Manipulation Extension, version 1.0.0 <https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf>`_ and `version 0.93 (draft from January 10, 2021) <https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.93.pdf>`_
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* `PMP Enhancements for memory access and execution prevention on Machine mode (Smepmp) version 0.9.3 <https://github.com/riscv/riscv-tee/blob/61455747230a26002d741f64879dd78cc9689323/Smepmp/Smepmp.pdf>`_
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Many features in the RISC-V specification are optional, and Ibex can be parametrized to enable or disable some of them.
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@ -35,8 +35,8 @@ In addition, the following instruction set extensions are available.
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- 2.0
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- optional
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* - **B**: Draft Extension for Bit Manipulation Instructions
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- 0.92 [#B_draft]_
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* - **B**: Standard Extension for Bit-Manipulation Instructions
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- 1.0.0 + 0.93 [#B_draft]_
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- optional
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* - **Zicsr**: Control and Status Register Instructions
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@ -59,7 +59,9 @@ See :ref:`PMP Enhancements<pmp-enhancements>` for more information on Ibex's exp
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.. rubric:: Footnotes
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.. [#B_draft] Note that while Ibex fully implements draft version 0.92 of the RISC-V Bit Manipulation Extension, this extension may change before being ratified as a standard by the RISC-V Foundation.
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.. [#B_draft] Ibex fully implements the ratified version 1.0.0 of the RISC-V Bit-Manipulation Extension including the Zba, Zbb, Zbc and Zbs sub-extensions.
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In addition, Ibex also supports the remaining Zbe, Zbf, Zbp, Zbr and Zbt sub-extensions as defined in draft version 0.93 of the RISC-V Bit-Manipulation Extension.
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Note that the latter sub-extensions may change before being ratified as a standard by the RISC-V Foundation.
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Ibex will be updated to match future versions of the specification.
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Prior to ratification this may involve backwards incompatible changes.
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Additionally, neither GCC or Clang have committed to maintaining support upstream for unratified versions of the specification.
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@ -7,7 +7,7 @@ ASIC Synthesis
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ASIC synthesis is supported for Ibex.
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The whole design is completely synchronous and uses positive-edge triggered flip-flops, except for the register file, which can be implemented either with latches or with flip-flops.
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See :ref:`register-file` for more details.
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The core occupies an area of roughly 24 kGE when using the latch-based register file and implementing the RV32IMC ISA, or 16 kGE when implementing the RV32EC ISA.
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The core occupies an area of roughly 24 kGE when using the latch-based register file and implementing the RV32IMC ISA, or 15 kGE when implementing the RV32EC ISA.
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FPGA Synthesis
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@ -64,44 +64,45 @@ Other blocks use the ALU for the following tasks:
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* It computes memory addresses for loads and stores with a Reg + Imm calculation
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* The LSU uses it to increment addresses when performing two accesses to handle an unaligned access
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Bit Manipulation Extension
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Support for the `RISC-V Bit Manipulation Extension (draft version 0.92 from November 8, 2019) <https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.92.pdf>`_ is optional. [#B_draft]_
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Bit-Manipulation Extension
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Support for the `RISC-V Bit-Manipulation Extension version 1.0.0 <https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf>`_ and `draft version 0.93 from January 10, 2021 <https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.93.pdf>`_ is optional. [#B_draft]_
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It can be enabled via the enumerated parameter ``RV32B`` defined in :file:`rtl/ibex_pkg.sv`.
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By default, this parameter is set to "ibex_pkg::RV32BNone" to disable the bit manipulation extension.
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By default, this parameter is set to "ibex_pkg::RV32BNone" to disable the bit-manipulation extension.
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There are two versions of the bit manipulation extension available:
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The balanced implementation comprises a set of sub-extensions aiming for good benefits at a reasonable area overhead.
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There are three versions of the bit-manipulation extension available:
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The balanced version comprises a set of sub-extensions aiming for good benefits at a reasonable area overhead.
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It can be selected by setting the ``RV32B`` parameter to "ibex_pkg::RV32BBalanced".
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The full implementation comprises all 32 bit instructions defined in the extension.
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This version can be selected by setting the ``RV32B`` parameter to "ibex_pkg::RV32BFull".
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The following table lists the implemented instructions in each version.
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The OTEarlGrey version comprises all sub-extensions except for the Zbe.
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This version can be selected by setting the ``RV32B`` parameter to "ibex_pkg::RV32BOTEarlGrey".
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The full version comprises all sub-extensions and can be selected by setting the ``RV32B`` parameter to "ibex_pkg::RV32BFull".
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The following table gives an overview of which sub-extensions are implemented in each version and of which instructions are implemented as multi-cycle instructions.
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Multi-cycle instructions are completed in 2 cycles.
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All remaining instructions complete in a single cycle.
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+---------------------------------+---------------+--------------------------+
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| Z-Extension | Version | Multi-Cycle Instructions |
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+=================================+===============+==========================+
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| Zbb (Base) | Balanced/Full | rol, ror[i] |
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+---------------------------------+---------------+--------------------------+
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| Zbs (Single-bit) | Balanced/Full | None |
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+---------------------------------+---------------+--------------------------+
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| Zbp (Permutation) | Full | None |
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+---------------------------------+---------------+--------------------------+
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| Zbe (Bit compress/decompress) | Full | All |
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+---------------------------------+---------------+--------------------------+
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| Zbf (Bit-field place) | Balanced/Full | All |
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+---------------------------------+---------------+--------------------------+
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| Zbc (Carry-less multiply) | Full | None |
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+---------------------------------+---------------+--------------------------+
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| Zbr (CRC) | Full | All |
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+---------------------------------+---------------+--------------------------+
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| Zbt (Ternary) | Balanced/Full | All |
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+---------------------------------+---------------+--------------------------+
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+--------------------------------+---------+----------+------------+------+--------------------+
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| Bit-Manipulation Sub-Extension | Spec. | Balanced | OTEarlGrey | Full | Multi-Cycle Instr. |
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+================================+=========+==========+============+======+====================+
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| Zba (Address generation) | v.1.0.0 | X | X | X | None |
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+--------------------------------+---------+----------+------------+------+--------------------+
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| Zbb (Base) | v.1.0.0 | X | X | X | rol, ror[i] |
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+--------------------------------+---------+----------+------------+------+--------------------+
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| Zbc (Carry-less multiply) | v.1.0.0 | | X | X | None |
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+--------------------------------+---------+----------+------------+------+--------------------+
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| Zbs (Single-bit) | v.1.0.0 | X | X | X | None |
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+--------------------------------+---------+----------+------------+------+--------------------+
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| Zbe (Bit compress/decompress) | v.0.93 | | | X | All |
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+--------------------------------+---------+----------+------------+------+--------------------+
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| Zbf (Bit-field place) | v.0.93 | X | X | X | All |
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+--------------------------------+---------+----------+------------+------+--------------------+
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| Zbp (Permutation) | v.0.93 | | X | X | None |
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+--------------------------------+---------+----------+------------+------+--------------------+
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| Zbr (CRC) | v.0.93 | | X | X | All |
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+--------------------------------+---------+----------+------------+------+--------------------+
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| Zbt (Ternary) | v.0.93 | X | X | X | All |
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+--------------------------------+---------+----------+------------+------+--------------------+
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The implementation of the B-extension comes with an area overhead of 1.8 to 3.0 kGE for the balanced version and 6.0 to 8.7 kGE for the full version.
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That corresponds to an approximate percentage increase in area of 9 to 14 % and 25 to 30 % for the balanced and full versions respectively.
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The ranges correspond to synthesis results generated using relaxed and maximum frequency targets respectively.
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The designs have been synthesized using Synopsys Design Compiler targeting TSMC 65 nm technology.
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The implementation of the Bit-Manipulation Extension comes with an area overhead of 2.7 kGE for the balanced version, 6.1 kGE for the OTEarlGrey version, and 7.5 kGE for the full version.
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These numbers were obtained by synthesizing the design with Yosys and relaxed timing constraints.
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.. _mult-div:
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@ -171,8 +172,9 @@ See :ref:`load-store-unit` for more details.
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.. rubric:: Footnotes
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.. [#B_draft] Ibex fully implements draft version 0.92 of the RISC-V Bit Manipulation Extension.
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This extension may change before being ratified as a standard by the RISC-V Foundation.
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.. [#B_draft] Ibex fully implements the ratified version 1.0.0 of the RISC-V Bit-Manipulation Extension including the Zba, Zbb, Zbc and Zbs sub-extensions.
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In addition, Ibex also supports the remaining Zbe, Zbf, Zbp, Zbr and Zbt sub-extensions as defined in draft version 0.93 of the RISC-V Bit-Manipulation Extension.
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Note that the latter sub-extensions may change before being ratified as a standard by the RISC-V Foundation.
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Ibex will be updated to match future versions of the specification.
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Prior to ratification this may involve backwards incompatible changes.
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Additionally, neither GCC or Clang have committed to maintaining support upstream for unratified versions of the specification.
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