[doc] Fix spelling of CoreMark

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
This commit is contained in:
Pirmin Vogel 2020-07-03 17:54:42 +02:00
parent d7284c2cbd
commit 414ff7eeb0
5 changed files with 24 additions and 24 deletions

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@ -23,15 +23,15 @@ These are configurations on which lowRISC is focusing for performance evaluation
| Config | "small" | "maxperf" | "maxperf-pmp-bmfull" |
| ------ | ------- | --------- | ---------------- |
| Features | RV32IMC, 3 cycle mult | RV32IMC, 1 cycle mult, Branch target ALU, Writeback stage | RV32IMCB, 1 cycle mult, Branch target ALU, Writeback stage, 16 PMP regions |
| Performance (Coremark/MHz) | 2.44 | 3.09 | 3.09 |
| Performance (CoreMark/MHz) | 2.44 | 3.09 | 3.09 |
| Area - Yosys (kGE) | 33.15 | 39.03 | 63.32 |
| Area - Commercial (estimated kGE) | ~27 | ~31 | ~50 |
| Verification status | Green | Amber | Amber |
Notes:
* Performance numbers are based on Cormark running on the Ibex Simple System [platform](examples/simple_system/README.md).
Note that Coremark was compiled without support for the B extension.
* Performance numbers are based on CoreMark running on the Ibex Simple System [platform](examples/simple_system/README.md).
Note that CoreMark was compiled without support for the B extension.
* Yosys synthesis area numbers are based on the Ibex basic synthesis [flow](syn/README.md).
* Commercial synthesis area numbers are a rough estimate of what might be achievable with a commercial synthesis flow and technology library.
* Verification status is a rough guide to the overall maturity of a particular configuration.

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@ -16,23 +16,23 @@ fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_simple
See examples/simple_system/README.md for full details.
## Coremark
## CoreMark
Coremark (https://www.eembc.org/coremark/ https://github.com/eembc/coremark) is
CoreMark (https://www.eembc.org/coremark/ https://github.com/eembc/coremark) is
an industry standard benchmark with results available for a wide variety of
systems.
The Coremark source is vendored into the Ibex repository at
`vendor/eembc_coremark`. Support structure and a makefile to build Coremark for
The CoreMark source is vendored into the Ibex repository at
`vendor/eembc_coremark`. Support structure and a makefile to build CoreMark for
running on simple system is found in `examples/sw/benchmarks/coremark`.
To build Coremark:
To build CoreMark:
```
make -C ./examples/sw/benchmarks/coremark/
```
To run Coremark (after building a suitable simulator binary, see above):
To run CoreMark (after building a suitable simulator binary, see above):
```
build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/Vibex_simple_system --meminit=ram,examples/sw/benchmarks/coremark/coremark.elf
@ -41,7 +41,7 @@ build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/Vibex_simple_system --memi
The simulator outputs the performance counter values observed for the benchmark
(the counts do not include anything from pre or post benchmark loops).
Coremark should output (to `ibex_simple_system.log`) something like the
CoreMark should output (to `ibex_simple_system.log`) something like the
following:
```
@ -62,30 +62,30 @@ seedcrc : 0xe9f5
Correct operation validated. See README.md for run and reporting rules.
```
A Coremark score is given as the number of iterations executed per second. The
Coremark binary is hard-coded to execute 10 iterations (see
A CoreMark score is given as the number of iterations executed per second. The
CoreMark binary is hard-coded to execute 10 iterations (see
`examples/sw/benchmarks/coremark/Makefile` if you wish to alter this). To obtain
a useful Coremark score from the simulation you need to choose a clock speed the
a useful CoreMark score from the simulation you need to choose a clock speed the
Ibex implementation you are interested in would run at, e.g. 100 MHz, taking
the above example:
* 10 iterations take 4244465 clock cycles
* So at 100 MHz Ibex would execute (100 * 10^6) / (4244465 / 10) = 235.6
Iterations in 1 second.
* Coremark (at 100 MHz) is 235.6
* CoreMark (at 100 MHz) is 235.6
Coremark/MHz is often used instead of a raw Coremark score. The example above
gives a Coremark/MHz of 2.36 (235.6 / 100 rounded to 2 decimal places).
CoreMark/MHz is often used instead of a raw CoreMark score. The example above
gives a CoreMark/MHz of 2.36 (235.6 / 100 rounded to 2 decimal places).
To directly produce Coremark/MHz from the number of iterations (I) and total
To directly produce CoreMark/MHz from the number of iterations (I) and total
ticks (T) use the follow formula:
```
Coremark/MHz = (10 ^ 6) * I / T
CoreMark/MHz = (10 ^ 6) * I / T
```
Note that `core_main.c` from Coremark has had a minor modification to prevent it
Note that `core_main.c` from CoreMark has had a minor modification to prevent it
from reporting an error if it executes for less than 10 seconds. This violates
the run reporting rules (though does not effect benchmark execution). It is
trivial to restore `core_main.c` to the version supplied by EEMBC in the
Coremark repository if an official result is desired.
CoreMark repository if an official result is desired.

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@ -160,7 +160,7 @@ ee_u32 default_num_contexts = 1;
Test for some common mistakes.
*/
void portable_init(core_portable *p, int *argc, char *argv[]) {
ee_printf("Ibex coremark platform init...\n");
ee_printf("Ibex CoreMark platform init...\n");
if (sizeof(ee_ptr_int) != sizeof(ee_u8 *)) {
ee_printf(
"ERROR! Please define ee_ptr_int to a type that holds a pointer!\n");
@ -181,7 +181,7 @@ void portable_fini(core_portable *p) {
coremark_mhz = (1000000.0f * (float)ITERATIONS) / elapsed;
ee_printf("Coremark / MHz: %f\n", coremark_mhz);
ee_printf("CoreMark / MHz: %f\n", coremark_mhz);
p->portable_id = 0;
}

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@ -76,7 +76,7 @@ extern unsigned int _stack_start;
*Imprtant* :
ee_ptr_int needs to be the data type used to hold pointers, otherwise
coremark may fail!!!
CoreMark may fail!!!
*/
typedef signed short ee_s16;
typedef unsigned short ee_u16;

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@ -114,7 +114,7 @@ module ibex_core #(
localparam bit DummyInstructions = SecureIbex;
// Speculative branch option, trades-off performance against timing.
// Setting this to 1 eases branch target critical paths significantly but reduces performance
// by ~3% (based on Coremark/MHz score).
// by ~3% (based on CoreMark/MHz score).
// Set by default in the max PMP config which has the tightest budget for branch target timing.
localparam bit SpecBranch = PMPEnable & (PMPNumRegions == 16);