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Update lowrisc_ip to lowRISC/opentitan@9ac4f9c8
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 9ac4f9c8b924b79eb7d3581b29346a612f705751 * Allow verilated top-levels to do work after a simulation completes (Rupert Swarbrick) * Add some missing dependencies on lowrisc:prim:assert (Rupert Swarbrick) Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
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f98ddabee1
commit
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6 changed files with 85 additions and 80 deletions
2
vendor/lowrisc_ip.lock.hjson
vendored
2
vendor/lowrisc_ip.lock.hjson
vendored
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@ -9,6 +9,6 @@
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upstream:
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{
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url: https://github.com/lowRISC/opentitan
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rev: 976d9b9c1f563173d9e4571c775b38e70cb1c5d4
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rev: 9ac4f9c8b924b79eb7d3581b29346a612f705751
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}
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}
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@ -36,8 +36,6 @@ void VerilatorSimCtrl::SetTop(VerilatedToplevel *top, CData *sig_clk,
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}
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int VerilatorSimCtrl::Exec(int argc, char **argv) {
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RegisterSignalHandler();
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bool exit_app = false;
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if (!ParseCommandArgs(argc, argv, exit_app)) {
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return 1;
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@ -55,7 +53,68 @@ int VerilatorSimCtrl::Exec(int argc, char **argv) {
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return 0;
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}
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bool VerilatorSimCtrl::ParseCommandArgs(int argc, char **argv, bool &exit_app) {
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const struct option long_options[] = {
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{"term-after-cycles", required_argument, nullptr, 'c'},
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{"trace", no_argument, nullptr, 't'},
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{"help", no_argument, nullptr, 'h'},
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{nullptr, no_argument, nullptr, 0}};
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while (1) {
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int c = getopt_long(argc, argv, ":c:th", long_options, nullptr);
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if (c == -1) {
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break;
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}
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// Disable error reporting by getopt
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opterr = 0;
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switch (c) {
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case 0:
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break;
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case 't':
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if (!tracing_possible_) {
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std::cerr << "ERROR: Tracing has not been enabled at compile time."
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<< std::endl;
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return false;
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}
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TraceOn();
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break;
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case 'c':
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term_after_cycles_ = atoi(optarg);
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break;
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case 'h':
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PrintHelp();
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exit_app = true;
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break;
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case ':': // missing argument
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std::cerr << "ERROR: Missing argument." << std::endl << std::endl;
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return false;
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case '?':
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default:;
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// Ignore unrecognized options since they might be consumed by
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// Verilator's built-in parsing below.
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}
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}
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// Pass args to verilator
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Verilated::commandArgs(argc, argv);
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// Parse arguments for all registered extensions
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for (auto it = extension_array_.begin(); it != extension_array_.end(); ++it) {
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if (!(*it)->ParseCLIArguments(argc, argv, exit_app)) {
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return false;
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if (exit_app) {
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return true;
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}
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}
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}
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return true;
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}
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void VerilatorSimCtrl::RunSimulation() {
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RegisterSignalHandler();
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// Print helper message for tracing
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if (TracingPossible()) {
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std::cout << "Tracing can be toggled by sending SIGUSR1 to this process:"
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@ -141,65 +200,6 @@ void VerilatorSimCtrl::SignalHandler(int sig) {
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}
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}
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bool VerilatorSimCtrl::ParseCommandArgs(int argc, char **argv, bool &exit_app) {
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const struct option long_options[] = {
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{"term-after-cycles", required_argument, nullptr, 'c'},
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{"trace", no_argument, nullptr, 't'},
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{"help", no_argument, nullptr, 'h'},
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{nullptr, no_argument, nullptr, 0}};
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while (1) {
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int c = getopt_long(argc, argv, ":c:th", long_options, nullptr);
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if (c == -1) {
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break;
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}
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// Disable error reporting by getopt
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opterr = 0;
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switch (c) {
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case 0:
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break;
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case 't':
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if (!tracing_possible_) {
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std::cerr << "ERROR: Tracing has not been enabled at compile time."
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<< std::endl;
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return false;
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}
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TraceOn();
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break;
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case 'c':
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term_after_cycles_ = atoi(optarg);
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break;
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case 'h':
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PrintHelp();
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exit_app = true;
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break;
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case ':': // missing argument
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std::cerr << "ERROR: Missing argument." << std::endl << std::endl;
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return false;
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case '?':
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default:;
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// Ignore unrecognized options since they might be consumed by
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// Verilator's built-in parsing below.
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}
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}
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// Pass args to verilator
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Verilated::commandArgs(argc, argv);
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// Parse arguments for all registered extensions
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for (auto it = extension_array_.begin(); it != extension_array_.end(); ++it) {
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if (!(*it)->ParseCLIArguments(argc, argv, exit_app)) {
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return false;
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if (exit_app) {
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return true;
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}
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}
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}
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return true;
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}
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void VerilatorSimCtrl::PrintHelp() const {
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std::cout << "Execute a simulation model for " << GetName() << "\n\n";
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if (tracing_possible_) {
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@ -46,23 +46,34 @@ class VerilatorSimCtrl {
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* SetTop() must be called before this function.
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*
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* This function performs the following tasks:
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* 1. Sets up a signal handler to enable tracing to be turned on/off during
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* a run by sending SIGUSR1 to the process
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* 2. Parses a C-style set of command line arguments.
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* 3. Runs the simulation
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* 1. Parses a C-style set of command line arguments (see ParseCommandArgs())
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* 2. Runs the simulation (see RunSimulation())
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*
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* @return a main()-compatible process exit code: 0 for success, 1 in case
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* of an error.
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*/
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int Exec(int argc, char **argv);
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/**
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* Parse command line arguments
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*
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* Process all recognized command-line arguments from argc/argv.
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*
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* @param argc, argv Standard C command line arguments
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* @param exit_app Indicate that program should terminate
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* @return Return code, true == success
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*/
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bool ParseCommandArgs(int argc, char **argv, bool &exit_app);
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/**
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* A helper function to execute a standard set of run commands.
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*
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* This function performs the following tasks:
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* 1. Prints some tracer-related helper messages
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* 2. Runs the simulation
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* 3. Prints some further helper messages and statistics once the simulation
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* 1. Sets up a signal handler to enable tracing to be turned on/off during
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* a run by sending SIGUSR1 to the process
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* 2. Prints some tracer-related helper messages
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* 3. Runs the simulation
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* 4. Prints some further helper messages and statistics once the simulation
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* has run to completion
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*/
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void RunSimulation();
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*/
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static void SignalHandler(int sig);
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/**
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* Parse command line arguments
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*
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* Process all recognized command-line arguments from argc/argv.
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*
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* @param argc, argv Standard C command line arguments
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* @param exit_app Indicate that program should terminate
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* @return Return code, true == success
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*/
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bool ParseCommandArgs(int argc, char **argv, bool &exit_app);
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/**
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* Print help how to use this tool
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*/
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@ -7,6 +7,8 @@ name: "lowrisc:prim_generic:clock_mux2"
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description: "two-input clock multiplexer primitive"
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filesets:
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files_rtl:
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depend:
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- lowrisc:prim:assert
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files:
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- rtl/prim_generic_clock_mux2.sv
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file_type: systemVerilogSource
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@ -7,6 +7,8 @@ name: "lowrisc:prim_generic:pad_wrapper"
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description: "Technology-independent pad wrapper implementation (for sim only!)"
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filesets:
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files_rtl:
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depend:
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- lowrisc:prim:assert
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files:
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- rtl/prim_generic_pad_wrapper.sv
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file_type: systemVerilogSource
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@ -8,6 +8,7 @@ description: "Single port RAM"
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filesets:
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files_rtl:
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depend:
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- lowrisc:prim:assert
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- lowrisc:prim:util_memload
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files:
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- rtl/prim_generic_ram_1p.sv
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