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New encoding, targeting Xpulpv2 now
This commit is contained in:
Andreas Traber
parent
d548ea579e
commit
4630c28884
3 changed files with 57 additions and 61 deletions
110
decoder.sv
110
decoder.sv
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@ -283,7 +283,7 @@ module riscv_decoder
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// offset from register
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regc_used_o = 1'b1;
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alu_op_b_mux_sel_o = `OP_B_REGC_OR_FWD;
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regc_mux_o = `REGC_S3;
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regc_mux_o = `REGC_RD;
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end
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// store size
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@ -482,21 +482,20 @@ module riscv_decoder
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mult_operator_o = `MUL_MAC32;
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regc_mux_o = `REGC_ZERO;
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end
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// commented since they currently clash with p.mac and p.msu
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//{6'b00_0001, 3'b001}: begin // mulh
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// regc_used_o = 1'b1;
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// regc_mux_o = `REGC_ZERO;
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// mult_signed_mode_o = 2'b11;
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// mult_int_en_o = 1'b1;
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// mult_operator_o = `MUL_H;
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//end
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//{6'b00_0001, 3'b010}: begin // mulhsu
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// regc_used_o = 1'b1;
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// regc_mux_o = `REGC_ZERO;
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// mult_signed_mode_o = 2'b01;
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// mult_int_en_o = 1'b1;
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// mult_operator_o = `MUL_H;
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//end
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{6'b00_0001, 3'b001}: begin // mulh
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regc_used_o = 1'b1;
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regc_mux_o = `REGC_ZERO;
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mult_signed_mode_o = 2'b11;
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mult_int_en_o = 1'b1;
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mult_operator_o = `MUL_H;
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end
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{6'b00_0001, 3'b010}: begin // mulhsu
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regc_used_o = 1'b1;
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regc_mux_o = `REGC_ZERO;
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mult_signed_mode_o = 2'b01;
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mult_int_en_o = 1'b1;
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mult_operator_o = `MUL_H;
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end
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{6'b00_0001, 3'b011}: begin // mulhu
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regc_used_o = 1'b1;
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regc_mux_o = `REGC_ZERO;
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@ -504,18 +503,6 @@ module riscv_decoder
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mult_int_en_o = 1'b1;
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mult_operator_o = `MUL_H;
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end
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{6'b00_0001, 3'b001}: begin // p.mac
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regc_used_o = 1'b1;
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regc_mux_o = `REGC_RD;
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mult_int_en_o = 1'b1;
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mult_operator_o = `MUL_MAC32;
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end
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{6'b00_0001, 3'b010}: begin // p.msu
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regc_used_o = 1'b1;
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regc_mux_o = `REGC_RD;
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mult_int_en_o = 1'b1;
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mult_operator_o = `MUL_MSU32;
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end
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{6'b00_0001, 3'b100}: begin // div
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alu_op_a_mux_sel_o = `OP_A_REGB_OR_FWD;
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alu_op_b_mux_sel_o = `OP_B_REGC_OR_FWD;
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@ -554,8 +541,19 @@ module riscv_decoder
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end
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// PULP specific instructions
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{6'b00_0010, 3'b000}: begin alu_operator_o = `ALU_ADD; bmask_b_mux_o = `BMASK_B_ONE; end // Average
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{6'b00_0010, 3'b001}: begin alu_operator_o = `ALU_ADDU; bmask_b_mux_o = `BMASK_B_ONE; end // Average Unsigned
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{6'b10_0001, 3'b000}: begin // p.mac
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regc_used_o = 1'b1;
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regc_mux_o = `REGC_RD;
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mult_int_en_o = 1'b1;
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mult_operator_o = `MUL_MAC32;
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end
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{6'b10_0001, 3'b001}: begin // p.msu
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regc_used_o = 1'b1;
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regc_mux_o = `REGC_RD;
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mult_int_en_o = 1'b1;
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mult_operator_o = `MUL_MSU32;
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end
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{6'b00_0010, 3'b010}: alu_operator_o = `ALU_SLETS; // Set Lower Equal Than
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{6'b00_0010, 3'b011}: alu_operator_o = `ALU_SLETU; // Set Lower Equal Than Unsigned
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{6'b00_0010, 3'b100}: alu_operator_o = `ALU_MIN; // Min
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@ -575,7 +573,7 @@ module riscv_decoder
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{6'b00_1000, 3'b110}: begin alu_operator_o = `ALU_EXTS; alu_vec_mode_o = `VEC_MODE8; end // Sign-extend Byte
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{6'b00_1000, 3'b111}: begin alu_operator_o = `ALU_EXT; alu_vec_mode_o = `VEC_MODE8; end // Zero-extend Byte
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{6'b00_1010, 3'b000}: alu_operator_o = `ALU_ABS; // p.abs
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{6'b00_0010, 3'b000}: alu_operator_o = `ALU_ABS; // p.abs
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{6'b00_1010, 3'b001}: begin // p.clip
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alu_operator_o = `ALU_CLIP;
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@ -714,21 +712,6 @@ module riscv_decoder
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6'b01101_0: begin alu_operator_o = `ALU_AND; imm_b_mux_sel_o = `IMMB_VS; end // pv.and
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6'b01110_0: begin alu_operator_o = `ALU_ABS; imm_b_mux_sel_o = `IMMB_VS; end // pv.abs
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6'b01111_0: begin // pv.extract
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alu_operator_o = `ALU_EXTS;
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end
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6'b10000_0: begin // pv.extractu
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alu_operator_o = `ALU_EXT;
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end
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6'b10001_0: begin // pv.insert
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alu_operator_o = `ALU_INS;
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regc_used_o = 1'b1;
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regc_mux_o = `REGC_RD;
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alu_op_b_mux_sel_o = `OP_B_REGC_OR_FWD;
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end
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// shuffle/pack
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6'b11000_0: begin // pv.shuffle
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alu_operator_o = `ALU_SHUF;
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@ -760,36 +743,51 @@ module riscv_decoder
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regc_mux_o = `REGC_RD;
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end
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6'b10010_0: begin // pv.dotsp
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mult_dot_en_o = 1'b1;
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mult_dot_signed_o = 2'b11;
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6'b01111_0: begin // pv.extract
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alu_operator_o = `ALU_EXTS;
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end
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6'b10011_0: begin // pv.dotup
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6'b10010_0: begin // pv.extractu
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alu_operator_o = `ALU_EXT;
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end
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6'b10110_0: begin // pv.insert
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alu_operator_o = `ALU_INS;
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regc_used_o = 1'b1;
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regc_mux_o = `REGC_RD;
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alu_op_b_mux_sel_o = `OP_B_REGC_OR_FWD;
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end
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6'b10000_0: begin // pv.dotup
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mult_dot_en_o = 1'b1;
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mult_dot_signed_o = 2'b00;
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end
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6'b10100_0: begin // pv.dotusp
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6'b10001_0: begin // pv.dotusp
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mult_dot_en_o = 1'b1;
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mult_dot_signed_o = 2'b01;
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end
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6'b10101_0: begin // pv.sdotsp
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6'b10011_0: begin // pv.dotsp
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mult_dot_en_o = 1'b1;
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mult_dot_signed_o = 2'b11;
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regc_used_o = 1'b1;
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regc_mux_o = `REGC_RD;
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end
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6'b10110_0: begin // pv.sdotup
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6'b10100_0: begin // pv.sdotup
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mult_dot_en_o = 1'b1;
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mult_dot_signed_o = 2'b00;
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regc_used_o = 1'b1;
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regc_mux_o = `REGC_RD;
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end
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6'b10111_0: begin // pv.sdotusp
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6'b10101_0: begin // pv.sdotusp
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mult_dot_en_o = 1'b1;
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mult_dot_signed_o = 2'b01;
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regc_used_o = 1'b1;
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regc_mux_o = `REGC_RD;
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end
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6'b10111_0: begin // pv.sdotsp
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mult_dot_en_o = 1'b1;
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mult_dot_signed_o = 2'b11;
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regc_used_o = 1'b1;
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regc_mux_o = `REGC_RD;
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end
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// comparisons, always have bit 26 set
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6'b00000_1: begin alu_operator_o = `ALU_EQ; imm_b_mux_sel_o = `IMMB_VS; end // pv.cmpeq
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@ -387,7 +387,6 @@ module riscv_id_stage
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unique case (regc_mux)
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`REGC_ZERO: regfile_addr_rc_id = '0;
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`REGC_RD: regfile_addr_rc_id = instr[`REG_D];
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`REGC_S3: regfile_addr_rc_id = instr[`REG_S3];
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`REGC_S1: regfile_addr_rc_id = instr[`REG_S1];
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default: regfile_addr_rc_id = '0;
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endcase
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@ -1173,7 +1172,7 @@ module riscv_id_stage
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// make sure that branch decision is valid when jumping
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assert property (
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@(posedge clk) (branch_in_ex_o) |-> (branch_decision_i !== 1'bx) );
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@(posedge clk) (branch_in_ex_o) |-> (branch_decision_i !== 1'bx) ) else $display("Branch decision is X");
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// the instruction delivered to the ID stage should always be valid
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assert property (
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@ -75,10 +75,9 @@
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`define REG_D 11:07
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`define REGC_ZERO 2'b00
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`define REGC_S1 2'b10
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`define REGC_RD 2'b01
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`define REGC_S3 2'b10
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`define REGC_S1 2'b11
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`define REGC_ZERO 2'b11
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//////////////////////////////////////////////////////////////////////////////
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