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https://github.com/openhwgroup/cve2.git
synced 2025-04-22 13:07:46 -04:00
[ibex, dv] Added new base, interrupt, debug and mem error sequences
Added an independent base test with following capabilities: * chooses between single run, multiples runs or infinite runs (existing sequence does this via the `num_of_interations` variable). * interval between runs can be fixed or random, with 0 delay between runs possible. For random intervals there should be a way to bias them more towards 0 delay (e.g. specify 75% of delays should 0 with the rest randomly chosen). Added an interrupt sequence that inherits from the above base sequence. It has following capabilities: * chooses the number of interrupts to raise * specifies the interval between interrupt being raised and dropped * a mask to specify interrupts that shouldn't be raised. Added a debug sequence with the only functionality to specify the interval between the debug request being raised and dropped Added a sequence to corrupt instruction and data memory. Signed-off-by: Prajwala Puttappa <prajwalaputtappa@lowrisc.org>
This commit is contained in:
Prajwala Puttappa
prajwalaputtappa
parent
c15f3b8888
commit
46c397501d
4 changed files with 250 additions and 2 deletions
227
dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv
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227
dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv
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@ -0,0 +1,227 @@
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typedef enum bit [1:0] {
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SingleRun, // Singl iteration
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InfiniteRuns, // Run forever until stop is specified
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MultipleRuns, // Multiple runs with configurable or randomizable iteration count
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InvalidRuns // Default state
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} run_type_e;
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typedef enum bit [1:0] {
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IsideErr, // Inject error in instruction side memory.
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DsideErr, // Inject error in data side memory.
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PickErr // Pick which memory to inject error in.
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} error_type_e;
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class core_base_new_seq #(type REQ = uvm_sequence_item) extends uvm_sequence #(REQ);
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// Default set to 50% for zero delay to be picked. Set to 100 if zero delay is required always.
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int unsigned zero_delay_pct = 50;
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rand bit zero_delays;
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rand int delay = 0;
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int unsigned iteration_cnt = 0;
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int unsigned max_delay = 500;
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virtual clk_rst_if clk_vif;
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bit stop_seq;
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bit seq_finished;
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rand run_type_e num_of_iterations = InvalidRuns;
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virtual core_ibex_dut_probe_if dut_vif;
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// Use this bit to start any unique sequence once
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bit start_seq = 0;
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`uvm_object_param_utils(core_base_new_seq#(REQ))
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function new (string name = "");
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super.new(name);
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if(!uvm_config_db#(virtual clk_rst_if)::get(null, "", "clk_if", clk_vif)) begin
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`uvm_fatal(get_full_name(), "Cannot get clk_if")
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end
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if (!uvm_config_db#(virtual core_ibex_dut_probe_if)::get(null, "", "dut_if", dut_vif)) begin
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`uvm_fatal(get_full_name(), "Cannot get dut_if")
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end
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endfunction
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constraint zero_delays_c {
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zero_delays dist {1 :/ zero_delay_pct,
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0 :/ 100 - zero_delay_pct};
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}
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constraint reasonable_delay_c {
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delay inside {[0 : max_delay]};
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}
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virtual task body();
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if(num_of_iterations == InvalidRuns) begin
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`DV_CHECK_MEMBER_RANDOMIZE_WITH_FATAL(num_of_iterations, num_of_iterations != InvalidRuns;)
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end
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`uvm_info(`gfn, $sformatf("Doing %s", num_of_iterations.name()), UVM_LOW)
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case (num_of_iterations)
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SingleRun: begin
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drive_stimulus(delay);
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end
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MultipleRuns: begin
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if(iteration_cnt == 0) begin
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`DV_CHECK_MEMBER_RANDOMIZE_WITH_FATAL(iteration_cnt,
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iteration_cnt > 0 && iteration_cnt <= 20; )
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end
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for (int i = 0; i <= iteration_cnt; i++) begin
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drive_stimulus(delay);
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end
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end
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InfiniteRuns: begin
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while (!stop_seq) begin
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drive_stimulus(delay);
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end
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seq_finished = 1'b1;
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end
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default: begin
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`uvm_fatal(`gfn, "Type of run not set")
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end
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endcase
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endtask: body
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task drive_stimulus(int unsigned delay);
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if(delay == 0) begin
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`DV_CHECK_MEMBER_RANDOMIZE_FATAL(zero_delays)
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if(zero_delays) begin
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delay = 0;
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end else begin
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`DV_CHECK_MEMBER_RANDOMIZE_FATAL(delay)
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end
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end
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clk_vif.wait_clks(delay);
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`uvm_info(get_full_name(), "Starting sequence...", UVM_MEDIUM)
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send_req();
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`uvm_info(get_full_name(), "Exiting sequence", UVM_MEDIUM)
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endtask: drive_stimulus
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virtual task send_req();
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`uvm_fatal(get_full_name(), "This task must be implemented in the extended class")
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endtask
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virtual task stop();
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stop_seq = 1'b1;
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`uvm_info(get_full_name(), "Stopping sequence", UVM_MEDIUM)
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wait (seq_finished == 1'b1);
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endtask
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endclass
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class irq_new_seq extends core_base_new_seq #(irq_seq_item);
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`uvm_object_utils(irq_new_seq)
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`uvm_object_new
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bit no_nmi;
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bit no_fast;
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bit no_external;
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bit no_timer;
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bit no_software;
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int max_delay = 500;
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int min_delay = 50;
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rand int interval = min_delay;
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constraint reasonable_interval_c {
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interval inside {[min_delay : max_delay]};
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}
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virtual task send_req();
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irq_seq_item irq;
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irq = irq_seq_item::type_id::create("irq");
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// Raise interrupts
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start_item(irq);
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`DV_CHECK_RANDOMIZE_WITH_FATAL(irq, num_of_interrupt > 1;
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if (no_nmi) {
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irq_nm == 0;
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}
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if (no_fast) {
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irq_fast == '0;
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}
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if (no_external) {
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irq_external == 0;
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}
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if (no_timer) {
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irq_timer == 0;
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}
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if (no_software) {
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irq_software == 0;
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})
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finish_item(irq);
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get_response(irq);
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`DV_CHECK_MEMBER_RANDOMIZE_FATAL(interval)
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clk_vif.wait_clks(interval);
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// Drop interrupts
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start_item(irq);
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`DV_CHECK_RANDOMIZE_WITH_FATAL(irq, num_of_interrupt == 0;)
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finish_item(irq);
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get_response(irq);
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endtask: send_req
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endclass: irq_new_seq
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// Simple debug sequence
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// debug_req is just a single bit sideband signal, use the interface to drive it directly
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class debug_new_seq extends core_base_new_seq#(irq_seq_item);
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`uvm_object_utils(debug_new_seq)
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`uvm_object_new
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int max_delay = 500;
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int min_delay = 75;
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rand int unsigned drop_delay = 0;
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virtual task body();
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dut_vif.dut_cb.debug_req <= 1'b0;
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if(drop_delay == 0) begin
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`DV_CHECK_MEMBER_RANDOMIZE_WITH_FATAL(drop_delay,
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drop_delay inside {[min_delay : max_delay]};)
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end
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super.body();
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endtask
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virtual task send_req();
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`uvm_info(get_full_name(), "Sending debug request", UVM_HIGH)
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dut_vif.dut_cb.debug_req <= 1'b1;
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clk_vif.wait_clks(drop_delay);
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dut_vif.dut_cb.debug_req <= 1'b0;
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endtask
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endclass
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class memory_error_seq extends core_base_new_seq#(irq_seq_item);
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core_ibex_vseq vseq;
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rand error_type_e err_type = PickErr;
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rand bit choose_side;
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`uvm_object_utils(memory_error_seq)
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`uvm_declare_p_sequencer(core_ibex_vseqr)
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function new (string name = "");
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super.new(name);
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vseq = core_ibex_vseq::type_id::create("vseq");
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endfunction
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virtual task send_req();
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case (err_type)
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IsideErr: begin
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vseq.instr_intf_seq.inject_error();
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end
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DsideErr: begin
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vseq.data_intf_seq.inject_error();
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end
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PickErr: begin
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`DV_CHECK_STD_RANDOMIZE_FATAL(choose_side)
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if (choose_side) begin
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vseq.instr_intf_seq.inject_error();
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end else begin
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vseq.data_intf_seq.inject_error();
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end
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end
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default: begin
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// DO nothing
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end
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endcase
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if(!start_seq) begin
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vseq.start(p_sequencer);
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start_seq = 1;
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end
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endtask
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endclass: memory_error_seq
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@ -1399,3 +1399,18 @@ class core_ibex_invalid_csr_test extends core_ibex_directed_test;
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endtask
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endclass
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class core_mem_err_test extends core_ibex_directed_test;
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memory_error_seq memory_error_seq_h;
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`uvm_component_utils(core_mem_err_test)
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`uvm_component_new
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virtual task send_stimulus();
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memory_error_seq_h = memory_error_seq::type_id::create("memory_error_seq_h");
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memory_error_seq_h.vseq.cfg = cfg;
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memory_error_seq_h.vseq.mem = mem;
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memory_error_seq_h.start(env.vseqr);
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endtask: send_stimulus
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endclass: core_mem_err_test
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@ -23,8 +23,11 @@ package core_ibex_test_pkg;
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bit [11:0] system_imm;
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} instr_t;
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typedef class core_ibex_vseq;
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`include "core_ibex_report_server.sv"
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`include "core_ibex_seq_lib.sv"
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`include "core_ibex_new_seq_lib.sv"
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`include "core_ibex_vseq.sv"
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`include "core_ibex_base_test.sv"
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`include "core_ibex_test_lib.sv"
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@ -22,12 +22,15 @@ class core_ibex_vseq extends uvm_sequence;
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`uvm_object_utils(core_ibex_vseq)
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`uvm_declare_p_sequencer(core_ibex_vseqr)
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`uvm_object_new
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virtual task body();
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function new (string name = "");
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super.new(name);
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instr_intf_seq = ibex_mem_intf_response_seq::type_id::create("instr_intf_seq");
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data_intf_seq = ibex_mem_intf_response_seq::type_id::create("data_intf_seq");
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data_intf_seq.is_dmem_seq = 1'b1;
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endfunction
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virtual task body();
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if (cfg.enable_irq_single_seq) begin
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irq_raise_single_seq_h = irq_raise_single_seq::type_id::create("irq_single_seq_h");
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irq_raise_single_seq_h.num_of_iterations = 1;
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