github-mirrors/cve2
1
0
Fork 0
mirror of https://github.com/openhwgroup/cve2.git synced 2025-04-22 04:57:25 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

[sw/fpga] coremark/link.ld update for FPGA sim

Browse source 
This commit updates link.ld RAM length to include max BRAM capacity
for Arty A7-35. It also changes coremark makefile to include a .vmem
output, which then can be used for FPGA implementations.

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
This commit is contained in:
Canberk Topal 2021-07-23 16:11:20 +01:00 • committed by Canberk Topal
parent 7c0b1ff160
commit 4b54d79fb4
3 changed files with 22 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

12
examples/fpga/artya7/README.md
View file

@ -45,6 +45,8 @@ For example, it can be for example `/opt/riscv/bin/riscv-none-embed-gcc` if the
This should produce a `led.vmem` file which is used in the synthesis to update the SRAM storage.
### Hardware
Run either of the following commands at the top level to build the respective hardware.
@ -61,6 +63,16 @@ fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:top_artya
This will create a directory `build` which contains the output files, including
the bitstream.
Initial memory parameter `SRAMInitFile` can be given to FuseSoc to specify which .vmem file to load the design with.
Example use case includes loading `coremark.vmem` which can be used for performance/power analysis.
Please see [CoreMark README](https://github.com/lowRISC/ibex/blob/master/examples/sw/benchmarks/README.md) for compiling CoreMark.
```
fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:top_artya7 --part xc7a100tcsg324-1 --SRAMInitFile=examples/sw/benchmarks/coremark/coremark.vmem
```
## Program
After the board is connected to the computer it can be programmed with:

5
examples/sw/benchmarks/coremark/ibex/core_portme.mak
View file

@ -6,7 +6,7 @@
RV_ISA = rv32im
OUTFILES = $(OPATH)coremark.dis $(OPATH)coremark.map
OUTFILES = $(OPATH)coremark.dis $(OPATH)coremark.map $(OPATH)coremark.vmem
NAME = coremark
PORT_CLEAN := $(OUTFILES)
@ -86,6 +86,9 @@ $(OPATH)$(PORT_DIR)/%$(OEXT) : %.s
port_postbuild:
riscv32-unknown-elf-objdump -SD $(OPATH)coremark.elf > $(OPATH)coremark.dis
riscv32-unknown-elf-objcopy -O binary $(OPATH)coremark.elf $(OPATH)coremark.bin
srec_cat $(OPATH)coremark.bin -binary -offset 0x0000 -byte-swap 4 -o $(OPATH)coremark.vmem -vmem
# FLAG : OPATH
# Path to the output folder. Default - current folder.

9
examples/sw/simple_system/common/link.ld
View file

@ -6,9 +6,12 @@ OUTPUT_ARCH(riscv)
MEMORY
{
/* 992 kB should be enough for anybody... */
ram : ORIGIN = 0x00100000, LENGTH = 0xF8000 /* 992 kB */
stack : ORIGIN = 0x001F8000, LENGTH = 0x8000 /* 32 kB */
/* Change this if you'd like different sizes. Arty A7-100(35) has a maximum of 607.5KB(225KB)
BRAM space. Configuration below is for maximum BRAM capacity with Artya A7-35 while letting
CoreMark run (.vmem of 152.8KB).
*/
ram : ORIGIN = 0x00100000, LENGTH = 0x30000 /* 192 kB */
stack : ORIGIN = 0x00130000, LENGTH = 0x8000 /* 32 kB */
}
/* Stack information variables */