github-mirrors/cve2
1
0
Fork 0
mirror of https://github.com/openhwgroup/cve2.git synced 2025-04-22 13:07:46 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Update cve2_core.sv to accomodate MRET instruction (#143)

Browse source 
Change the timing of rvfi_id_done to accomodate MRET instruction. The signal rvfi_valid is a single clock delayed from rvfi_id_done
This commit is contained in:
Lee Hoff 2023-09-20 10:47:22 -04:00 • committed by GitHub
parent 4be52dedc2
commit 4e11d547fd
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
1 changed files with 4 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

6
rtl/cve2_core.sv
View file

@ -947,8 +947,10 @@ module cve2_core import cve2_pkg::*; #(
// Factor in exceptions taken in ID so RVFI tracking picks up flushed instructions that took
// a trap
assign rvfi_id_done = instr_id_done | (id_stage_i.controller_i.rvfi_flush_next &
id_stage_i.controller_i.exc_req_d);
// MRET causes MSTATUS to get written one clock later. Fix rvfi_valid when executing MRET
assign rvfi_id_done = (instr_id_done & !id_stage_i.controller_i.mret_insn)|
id_stage_i.csr_restore_mret_id_o |
(id_stage_i.controller_i.rvfi_flush_next & id_stage_i.controller_i.exc_req_d);
// Without writeback stage first RVFI stage is output stage so simply valid the cycle after
// instruction leaves ID/EX (and so has retired)