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[rtl] Add RVFI IXL interface

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Following the RISC-V Formal Interface (RVFI) specification the output is
added to set the value of MXL/SXL/UXL of the current privilege level.
This commit is contained in:
Tobias Wölfel 2020-02-24 12:08:23 +01:00 • committed by Philipp Wagner
parent 66687e927c
commit 4e7b981911
7 changed files with 28 additions and 13 deletions
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1
dv/uvm/core_ibex/env/core_ibex_rvfi_if.sv vendored
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@ -11,6 +11,7 @@ interface core_ibex_rvfi_if(input logic clk);
logic halt;
logic intr;
logic [1:0] mode;
logic [1:0] ixl;
logic [4:0] rs1_addr;
logic [4:0] rs2_addr;
logic [31:0] rs1_rdata;

1
dv/uvm/core_ibex/tb/core_ibex_tb_top.sv
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@ -101,6 +101,7 @@ module core_ibex_tb_top;
assign rvfi_if.trap = dut.rvfi_trap;
assign rvfi_if.intr = dut.rvfi_intr;
assign rvfi_if.mode = dut.rvfi_mode;
assign rvfi_if.ixl = dut.rvfi_ixl;
assign rvfi_if.rs1_addr = dut.rvfi_rs1_addr;
assign rvfi_if.rs2_addr = dut.rvfi_rs2_addr;
assign rvfi_if.rs1_rdata = dut.rvfi_rs1_rdata;

6
rtl/ibex_core.sv
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@ -80,6 +80,7 @@ module ibex_core #(
output logic rvfi_halt,
output logic rvfi_intr,
output logic [ 1:0] rvfi_mode,
output logic [ 1:0] rvfi_ixl,
output logic [ 4:0] rvfi_rs1_addr,
output logic [ 4:0] rvfi_rs2_addr,
output logic [ 4:0] rvfi_rs3_addr,
@ -979,6 +980,7 @@ module ibex_core #(
logic rvfi_stage_halt [RVFI_STAGES-1:0];
logic rvfi_stage_intr [RVFI_STAGES-1:0];
logic [ 1:0] rvfi_stage_mode [RVFI_STAGES-1:0];
logic [ 1:0] rvfi_stage_ixl [RVFI_STAGES-1:0];
logic [ 4:0] rvfi_stage_rs1_addr [RVFI_STAGES-1:0];
logic [ 4:0] rvfi_stage_rs2_addr [RVFI_STAGES-1:0];
logic [ 4:0] rvfi_stage_rs3_addr [RVFI_STAGES-1:0];
@ -1004,6 +1006,7 @@ module ibex_core #(
assign rvfi_halt = rvfi_stage_halt [RVFI_STAGES-1];
assign rvfi_intr = rvfi_stage_intr [RVFI_STAGES-1];
assign rvfi_mode = rvfi_stage_mode [RVFI_STAGES-1];
assign rvfi_ixl = rvfi_stage_ixl [RVFI_STAGES-1];
assign rvfi_rs1_addr = rvfi_stage_rs1_addr [RVFI_STAGES-1];
assign rvfi_rs2_addr = rvfi_stage_rs2_addr [RVFI_STAGES-1];
assign rvfi_rs3_addr = rvfi_stage_rs3_addr [RVFI_STAGES-1];
@ -1065,6 +1068,7 @@ module ibex_core #(
rvfi_stage_order[i] <= '0;
rvfi_stage_insn[i] <= '0;
rvfi_stage_mode[i] <= {PRIV_LVL_M};
rvfi_stage_ixl[i] <= CSR_MISA_MXL;
rvfi_stage_rs1_addr[i] <= '0;
rvfi_stage_rs2_addr[i] <= '0;
rvfi_stage_rs3_addr[i] <= '0;
@ -1092,6 +1096,7 @@ module ibex_core #(
rvfi_stage_order[i] <= rvfi_order + 64'(rvfi_valid);
rvfi_stage_insn[i] <= rvfi_insn_id;
rvfi_stage_mode[i] <= {priv_mode_id};
rvfi_stage_ixl[i] <= CSR_MISA_MXL;
rvfi_stage_rs1_addr[i] <= rvfi_rs1_addr_d;
rvfi_stage_rs2_addr[i] <= rvfi_rs2_addr_d;
rvfi_stage_rs3_addr[i] <= rvfi_rs3_addr_d;
@ -1116,6 +1121,7 @@ module ibex_core #(
rvfi_stage_order[i] <= rvfi_stage_order[i-1];
rvfi_stage_insn[i] <= rvfi_stage_insn[i-1];
rvfi_stage_mode[i] <= rvfi_stage_mode[i-1];
rvfi_stage_ixl[i] <= rvfi_stage_ixl[i-1];
rvfi_stage_rs1_addr[i] <= rvfi_stage_rs1_addr[i-1];
rvfi_stage_rs2_addr[i] <= rvfi_stage_rs2_addr[i-1];
rvfi_stage_rs3_addr[i] <= rvfi_stage_rs3_addr[i-1];

3
rtl/ibex_core_tracing.sv
View file

@ -83,6 +83,7 @@ module ibex_core_tracing #(
logic rvfi_halt;
logic rvfi_intr;
logic [ 1:0] rvfi_mode;
logic [ 1:0] rvfi_ixl;
logic [ 4:0] rvfi_rs1_addr;
logic [ 4:0] rvfi_rs2_addr;
logic [ 4:0] rvfi_rs3_addr;
@ -158,6 +159,7 @@ module ibex_core_tracing #(
.rvfi_halt,
.rvfi_intr,
.rvfi_mode,
.rvfi_ixl,
.rvfi_rs1_addr,
.rvfi_rs2_addr,
.rvfi_rs3_addr,
@ -192,6 +194,7 @@ module ibex_core_tracing #(
.rvfi_halt,
.rvfi_intr,
.rvfi_mode,
.rvfi_ixl,
.rvfi_rs1_addr,
.rvfi_rs2_addr,
.rvfi_rs3_addr,

25
rtl/ibex_cs_registers.sv
View file

@ -117,20 +117,19 @@ module ibex_cs_registers #(
import ibex_pkg::*;
// misa
localparam logic [1:0] MXL = 2'd1; // M-XLEN: XLEN in M-Mode for RV32
localparam logic [31:0] MISA_VALUE =
(0 << 0) // A - Atomic Instructions extension
| (1 << 2) // C - Compressed extension
| (0 << 3) // D - Double precision floating-point extension
| (32'(RV32E) << 4) // E - RV32E base ISA
| (0 << 5) // F - Single precision floating-point extension
| (32'(!RV32E) << 8) // I - RV32I/64I/128I base ISA
| (32'(RV32M) << 12) // M - Integer Multiply/Divide extension
| (0 << 13) // N - User level interrupts supported
| (0 << 18) // S - Supervisor mode implemented
| (1 << 20) // U - User mode implemented
| (0 << 23) // X - Non-standard extensions present
| (32'(MXL) << 30); // M-XLEN
(0 << 0) // A - Atomic Instructions extension
| (1 << 2) // C - Compressed extension
| (0 << 3) // D - Double precision floating-point extension
| (32'(RV32E) << 4) // E - RV32E base ISA
| (0 << 5) // F - Single precision floating-point extension
| (32'(!RV32E) << 8) // I - RV32I/64I/128I base ISA
| (32'(RV32M) << 12) // M - Integer Multiply/Divide extension
| (0 << 13) // N - User level interrupts supported
| (0 << 18) // S - Supervisor mode implemented
| (1 << 20) // U - User mode implemented
| (0 << 23) // X - Non-standard extensions present
| (32'(CSR_MISA_MXL) << 30); // M-XLEN
typedef struct packed {
logic mie;

3
rtl/ibex_pkg.sv
View file

@ -472,6 +472,9 @@ parameter int unsigned CSR_MSTATUS_MPP_BIT_HIGH = 12;
parameter int unsigned CSR_MSTATUS_MPRV_BIT = 17;
parameter int unsigned CSR_MSTATUS_TW_BIT = 21;
// CSR machine ISA
parameter logic [1:0] CSR_MISA_MXL = 2'd1; // M-XLEN: XLEN in M-Mode for RV32
// CSR interrupt pending/enable bits
parameter int unsigned CSR_MSIX_BIT = 3;
parameter int unsigned CSR_MTIX_BIT = 7;

2
rtl/ibex_tracer.sv
View file

@ -46,6 +46,7 @@ module ibex_tracer (
input logic rvfi_halt,
input logic rvfi_intr,
input logic [ 1:0] rvfi_mode,
input logic [ 1:0] rvfi_ixl,
input logic [ 4:0] rvfi_rs1_addr,
input logic [ 4:0] rvfi_rs2_addr,
input logic [ 4:0] rvfi_rs3_addr,
@ -72,6 +73,7 @@ module ibex_tracer (
logic unused_rvfi_halt = rvfi_halt;
logic unused_rvfi_intr = rvfi_intr;
logic [ 1:0] unused_rvfi_mode = rvfi_mode;
logic [ 1:0] unused_rvfi_ixl = rvfi_ixl;
import ibex_tracer_pkg::*;