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Added pv.ball instruction

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This commit is contained in:
Andreas Traber 2016-02-25 14:21:50 +01:00
parent e423b2c197
commit 4efa86705c
4 changed files with 9 additions and 3 deletions
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5
alu.sv
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@ -178,7 +178,7 @@ module riscv_alu
begin
comparison_result_o = is_equal;
case (operator_i)
unique case (operator_i)
`ALU_EQ: comparison_result_o = is_equal;
`ALU_NE: comparison_result_o = ~is_equal;
`ALU_GTS, `ALU_GTU: comparison_result_o = is_greater;
@ -188,6 +188,9 @@ module riscv_alu
`ALU_SLETS,
`ALU_SLETU,
`ALU_LES, `ALU_LEU: comparison_result_o = ~is_greater;
`ALU_EQALL: comparison_result_o = (operand_a_i == 32'hFFFF_FFFF);
default: ;
endcase
end

1
decoder.sv
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@ -227,6 +227,7 @@ module riscv_decoder
3'b101: alu_operator_o = `ALU_GES;
3'b110: alu_operator_o = `ALU_LTU;
3'b111: alu_operator_o = `ALU_GEU;
3'b010: alu_operator_o = `ALU_EQALL;
default: begin
illegal_insn_o = 1'b1;

1
ex_stage.sv
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@ -14,6 +14,7 @@
// Additional contributions by: //
// Igor Loi - igor.loi@unibo.it //
// Sven Stucki - svstucki@student.ethz.ch //
// Andreas Traber - atraber@iis.ee.ethz.ch //
// //
// Design Name: Excecute stage //
// Project Name: RI5CY //

5
include/riscv_defines.sv
View file

@ -93,8 +93,8 @@
`define ALU_AVG 6'b100010
`define ALU_AVGU 6'b100011
`define ALU_XOR 6'b001110
`define ALU_OR 6'b001111
`define ALU_XOR 6'b011011
`define ALU_OR 6'b011010
`define ALU_AND 6'b010101
// Shifts
@ -133,6 +133,7 @@
`define ALU_GEU 6'b001011
`define ALU_EQ 6'b001100
`define ALU_NE 6'b001101
`define ALU_EQALL 6'b001110
// Set Lower Than operations
`define ALU_SLTS 6'b000010