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Simplify instr core interface
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parent
adb40aef43
commit
4f06b67e65
2 changed files with 29 additions and 45 deletions
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@ -925,7 +925,7 @@ module controller
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// note: this is done intentionally before checking RVC decoding, to
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// suppress wrong (and annoying) messages during simulation
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if (illegal_insn_o) begin
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$warning("Illegal instruction (core %0d) at PC 0x%h:", $time, riscv_core.core_id_i);
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$warning("%t: Illegal instruction (core %0d) at PC 0x%h:", $time, riscv_core.core_id_i);
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//prettyPrintInstruction(instr_rdata_i, id_stage.current_pc_id_i);
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end
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end
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@ -1152,6 +1152,7 @@ module controller
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end
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end
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// flush the pipeline, insert NOP into EX stage
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FLUSH_EX:
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begin
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halt_if = 1'b1;
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@ -1161,6 +1162,7 @@ module controller
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ctrl_fsm_ns = FLUSH_WB;
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end
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// flush the pipeline, insert NOP into EX and WB stage
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FLUSH_WB:
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begin
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halt_if = 1'b1;
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@ -42,7 +42,7 @@ module instr_core_interface
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input logic [31:0] instr_rdata_i
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);
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enum logic [1:0] {IDLE, PENDING, WAIT_RVALID, WAIT_GNT } CS, NS;
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enum logic [1:0] {IDLE, WAIT_RVALID, WAIT_GNT } CS, NS;
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logic [31:0] rdata_Q;
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@ -61,11 +61,8 @@ module instr_core_interface
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begin
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CS <= NS;
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if (instr_req_o && instr_gnt_i)
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addr_Q <= instr_addr_o;
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if (wait_gnt)
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addr_Q <= addr_i;
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addr_Q <= instr_addr_o;
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if (instr_rvalid_i)
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rdata_Q <= instr_rdata_i;
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@ -81,6 +78,7 @@ module instr_core_interface
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rdata_o = instr_rdata_i;
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instr_addr_o = addr_i;
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wait_gnt = 1'b0;
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NS = CS;
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unique case(CS)
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// default state, not waiting for requested data
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@ -88,15 +86,16 @@ module instr_core_interface
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begin
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rdata_o = rdata_Q;
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NS = IDLE;
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instr_req_o = req_i;
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instr_req_o = 1'b0;
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if(req_i) begin
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instr_req_o = 1'b1;
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wait_gnt = 1'b1;
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if(instr_gnt_i) //~> granted request
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NS = PENDING;
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NS = WAIT_RVALID;
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else begin //~> got a request but no grant
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NS = WAIT_GNT;
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wait_gnt = 1'b1;
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end
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end
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end // case: IDLE
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@ -108,52 +107,35 @@ module instr_core_interface
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instr_req_o = 1'b1;
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if(instr_gnt_i)
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NS = PENDING;
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NS = WAIT_RVALID;
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else
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begin
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NS = WAIT_GNT;
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end
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end // case: WAIT_GNT
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// we got a grant, so now we wait for the rvalid
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PENDING:
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begin
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if (instr_rvalid_i) begin
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NS = IDLE;
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instr_req_o = req_i;
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if (req_i) begin
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if (instr_gnt_i) begin
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NS = PENDING;
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end else begin
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NS = WAIT_GNT;
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wait_gnt = 1'b1;
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end
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end
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end else begin
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NS = WAIT_RVALID;
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instr_req_o = 1'b0;
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end
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end // case: PENDING
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// we wait for rvalid, after that we are ready to serve a new request
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WAIT_RVALID :
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begin
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NS = WAIT_RVALID;
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instr_req_o = 1'b0;
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if (instr_rvalid_i) begin
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NS = IDLE;
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instr_req_o = req_i;
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if (req_i) begin
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// prepare for next request
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instr_req_o = 1'b1;
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if (req_i) begin
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if (instr_gnt_i)
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NS = PENDING;
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else begin
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NS = WAIT_GNT;
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wait_gnt = 1'b1;
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if (instr_rvalid_i) begin
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wait_gnt = 1'b1;
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if (instr_gnt_i) begin
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NS = WAIT_RVALID;
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end else begin
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NS = WAIT_GNT;
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end
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end
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end else begin
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// just wait for rvalid and go back to IDLE, no new request
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// requested
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instr_req_o = 1'b0;
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if (instr_rvalid_i) begin
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NS = IDLE;
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end
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end
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end // case: WAIT_RVALID
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