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[rtl] Fixes for single-cycle mutiply

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* single cycle multiplier configuration needlessly stalled for a cycle
* mult_hold wasn't being set in mult state machine in single cycle
  multiplier
This commit is contained in:
Greg Chadwick 2020-03-10 17:52:56 +00:00
parent 6be55207f3
commit 4f31a0e6e8
2 changed files with 17 additions and 3 deletions
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10
rtl/ibex_id_stage.sv
View file

@ -614,9 +614,13 @@ module ibex_id_stage #(
end
multdiv_en_dec: begin
// MUL or DIV operation
id_fsm_d = MULTI_CYCLE;
rf_we_raw = 1'b0;
stall_multdiv = 1'b1;
if (~ex_valid_i) begin
// When single-cycle multiply is configured mul can finish in the first cycle so
// only enter MULTI_CYCLE state if a result isn't immediately available
id_fsm_d = MULTI_CYCLE;
rf_we_raw = 1'b0;
stall_multdiv = 1'b1;
end
end
branch_in_dec: begin
// cond branch operation

10
rtl/ibex_multdiv_fast.sv
View file

@ -111,6 +111,10 @@ module ibex_multdiv_fast #(
end
end
`ASSERT_KNOWN(DivEnKnown, div_en_internal);
`ASSERT_KNOWN(MultEnKnown, mult_en_internal);
`ASSERT_KNOWN(MultDivEnKnown, multdiv_en);
assign multdiv_en = mult_en_internal | div_en_internal;
assign intermediate_val_d = div_en_i ? op_remainder_d : mac_res_d;
@ -183,6 +187,8 @@ module ibex_multdiv_fast #(
mult_valid = mult_en_i;
mult_state_d = MULL;
mult_hold = 1'b0;
unique case (mult_state_q)
MULL: begin
@ -190,6 +196,8 @@ module ibex_multdiv_fast #(
mac_res_d = mac_res;
mult_valid = 1'b0;
mult_state_d = MULH;
end else begin
mult_hold = ~multdiv_ready_id_i;
end
end
@ -207,6 +215,8 @@ module ibex_multdiv_fast #(
mult_state_d = MULL;
mult_valid = 1'b1;
mult_hold = ~multdiv_ready_id_i;
end
default: begin