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add missing signal decl

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This commit is contained in:
Davide Schiavone 2022-08-11 08:56:53 +02:00
parent 0ae2d4d394
commit 5039e60cde
1 changed files with 1 additions and 0 deletions
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rtl/ibex_core.sv
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@ -361,6 +361,7 @@ module ibex_core import ibex_pkg::*; #(
logic clk;
logic fetch_enable;
logic wake_from_sleep;
cve2_sleep_unit sleep_unit_i (
// Clock, reset interface