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Explicitly set alu_op_x_mux_sel in decoder

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To make the regfile address check in RV32E not triggering false alarms
when accessing reg x16 - x31, the decoder should only set the muxes
for the regfile output when the instruction actually requires the
regfile output.

It is cleaner to explicitly set the `alu_op_x_mux_sel` signals to
`OP_X_REG_X` instead of relying on the default assignment if they
are really needed.
This commit is contained in:
Pirmin Vogel 2019-07-03 15:19:09 +01:00
parent 9ed49b9a17
commit 5093e0a0d2
1 changed files with 17 additions and 6 deletions
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23
rtl/ibex_decoder.sv
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@ -168,8 +168,8 @@ module ibex_decoder #(
jump_set_o = 1'b0; jump_set_o = 1'b0;
branch_in_dec_o = 1'b0; branch_in_dec_o = 1'b0;
alu_operator_o = ALU_SLTU; alu_operator_o = ALU_SLTU;
alu_op_a_mux_sel_o = OP_A_REG_A; alu_op_a_mux_sel_o = OP_A_IMM;
alu_op_b_mux_sel_o = OP_B_REG_B; alu_op_b_mux_sel_o = OP_B_IMM;
imm_a_mux_sel_o = IMM_A_ZERO; imm_a_mux_sel_o = IMM_A_ZERO;
imm_b_mux_sel_o = IMM_B_I; imm_b_mux_sel_o = IMM_B_I;
@ -253,6 +253,9 @@ module ibex_decoder #(
OPCODE_BRANCH: begin // Branch OPCODE_BRANCH: begin // Branch
branch_in_dec_o = 1'b1; branch_in_dec_o = 1'b1;
if (instr_new_i) begin if (instr_new_i) begin
// Evaluate branch condition
alu_op_a_mux_sel_o = OP_A_REG_A;
alu_op_b_mux_sel_o = OP_B_REG_B;
unique case (instr[14:12]) unique case (instr[14:12])
3'b000: alu_operator_o = ALU_EQ; 3'b000: alu_operator_o = ALU_EQ;
3'b001: alu_operator_o = ALU_NE; 3'b001: alu_operator_o = ALU_NE;
@ -277,9 +280,11 @@ module ibex_decoder #(
//////////////// ////////////////
OPCODE_STORE: begin OPCODE_STORE: begin
data_req_o = 1'b1; alu_op_a_mux_sel_o = OP_A_REG_A;
data_we_o = 1'b1; alu_op_b_mux_sel_o = OP_B_REG_B;
alu_operator_o = ALU_ADD; data_req_o = 1'b1;
data_we_o = 1'b1;
alu_operator_o = ALU_ADD;
if (!instr[14]) begin if (!instr[14]) begin
// offset from immediate // offset from immediate
@ -302,6 +307,7 @@ module ibex_decoder #(
end end
OPCODE_LOAD: begin OPCODE_LOAD: begin
alu_op_a_mux_sel_o = OP_A_REG_A;
data_req_o = 1'b1; data_req_o = 1'b1;
regfile_wdata_sel_o = RF_WD_LSU; regfile_wdata_sel_o = RF_WD_LSU;
regfile_we = 1'b1; regfile_we = 1'b1;
@ -372,6 +378,7 @@ module ibex_decoder #(
end end
OPCODE_OPIMM: begin // Register-Immediate ALU Operations OPCODE_OPIMM: begin // Register-Immediate ALU Operations
alu_op_a_mux_sel_o = OP_A_REG_A;
alu_op_b_mux_sel_o = OP_B_IMM; alu_op_b_mux_sel_o = OP_B_IMM;
imm_b_mux_sel_o = IMM_B_I; imm_b_mux_sel_o = IMM_B_I;
regfile_we = 1'b1; regfile_we = 1'b1;
@ -408,7 +415,9 @@ module ibex_decoder #(
end end
OPCODE_OP: begin // Register-Register ALU operation OPCODE_OP: begin // Register-Register ALU operation
regfile_we = 1'b1; alu_op_a_mux_sel_o = OP_A_REG_A;
alu_op_b_mux_sel_o = OP_B_REG_B;
regfile_we = 1'b1;
if (instr[31]) begin if (instr[31]) begin
illegal_insn = 1'b1; illegal_insn = 1'b1;
@ -503,6 +512,7 @@ module ibex_decoder #(
// an illegal instruction. // an illegal instruction.
if (instr[14:12] == 3'b000) begin if (instr[14:12] == 3'b000) begin
alu_operator_o = ALU_ADD; // nop alu_operator_o = ALU_ADD; // nop
alu_op_a_mux_sel_o = OP_A_REG_A;
alu_op_b_mux_sel_o = OP_B_IMM; alu_op_b_mux_sel_o = OP_B_IMM;
regfile_we = 1'b0; regfile_we = 1'b0;
end else begin end else begin
@ -513,6 +523,7 @@ module ibex_decoder #(
OPCODE_SYSTEM: begin OPCODE_SYSTEM: begin
if (instr[14:12] == 3'b000) begin if (instr[14:12] == 3'b000) begin
// non CSR related SYSTEM instructions // non CSR related SYSTEM instructions
alu_op_a_mux_sel_o = OP_A_REG_A;
alu_op_b_mux_sel_o = OP_B_IMM; alu_op_b_mux_sel_o = OP_B_IMM;
unique case (instr[31:20]) unique case (instr[31:20])
12'h000: // ECALL 12'h000: // ECALL