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Another compressed instruction, include guards for verilator

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Sven Stucki 2015-07-21 17:57:49 +02:00
parent 45f23be416
commit 509c13dff8
2 changed files with 8 additions and 0 deletions
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4
compressed_decoder.sv
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@ -82,6 +82,10 @@ module compressed_decoder
// c.sltr
// c.srl -> srl rd', rd', rs2'
5'b00101: instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b101, 2'b01, instr_i[9:7], `OPCODE_OP};
// c.sllr -> sll rd', rs1', rd'
5'b01100: instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[4:2], 3'b001, 2'b01, instr_i[4:2], `OPCODE_OP};
// c.srlr
// c.sltr
// c.sltur -> sltu rd', rs1', rd'
5'b01111: instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b011, 2'b01, instr_i[4:2], `OPCODE_OP};
default: illegal_instr_o = 1'b1;

4
include/defines.sv
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@ -29,6 +29,8 @@
// http://patorjk.com/software/taag/#p=display&v=0&f=Standard&t=Fancy%20ASCII%20Art
////////////////////////////////////////////////////////////////////////////////
`ifndef _CORE_DEFINES
`define _CORE_DEFINES
////////////////////////////////////////////////
@ -383,3 +385,5 @@ endfunction // prettyPrintInstruction
//`define TCDM_ADDR_PRECAL
//`define BRANCH_PREDICTION
`endif