[rtl] Fix lint issues

rtl/ibex_cs_registers.sv

@@ -1282,7 +1282,7 @@ module ibex_cs_registers #(
 
   if (DbgTriggerEn) begin : gen_trigger_regs
     localparam int unsigned DbgHwNumLen = DbgHwBreakNum > 1 ? $clog2(DbgHwBreakNum) : 1;
-    localparam int MaxTselect = DbgHwBreakNum - 1;
+    localparam int unsigned MaxTselect = DbgHwBreakNum - 1;
 
     // Register values
     logic [DbgHwNumLen-1:0]   tselect_d, tselect_q;
@@ -1313,6 +1313,7 @@ module ibex_cs_registers #(
     // select register. Only allow changes to the register if it is within the supported region.
     assign tselect_d = (csr_wdata_int < DbgHwBreakNum) ? csr_wdata_int[DbgHwNumLen-1:0] :
                                                          MaxTselect[DbgHwNumLen-1:0];
+
     // tmatch_control is enabled when the execute bit is set
     assign tmatch_control_d = csr_wdata_int[2];
     assign tmatch_value_d   = csr_wdata_int[31:0];

rtl/ibex_id_stage.sv

@@ -671,9 +671,12 @@ module ibex_id_stage #(
     // Branches always take two cycles in fixed time execution mode, with or without the branch
     // target ALU (to avoid a path from the branch decision into the branch target ALU operand
     // muxing).
-    assign branch_set_raw      = (BranchTargetALU && !data_ind_timing_i) ? branch_set_raw_d : branch_set_raw_q;
+    assign branch_set_raw      = (BranchTargetALU && !data_ind_timing_i) ? branch_set_raw_d :
+                                                                           branch_set_raw_q;
+
     // Use the speculative branch signal when BTALU is enabled
-    assign branch_set_raw_spec = (BranchTargetALU && !data_ind_timing_i) ? branch_spec : branch_set_raw_q;
+    assign branch_set_raw_spec = (BranchTargetALU && !data_ind_timing_i) ? branch_spec :
+                                                                           branch_set_raw_q;
   end
 
   // Track whether the current instruction in ID/EX has done a branch or jump set.
@@ -691,10 +694,10 @@ module ibex_id_stage #(
   // the _raw signals from the state machine may be asserted for multiple cycles when
   // instr_executing_spec is asserted and instr_executing is not asserted. This may occur where
   // a memory error is seen or a there are outstanding memory accesses (indicate a load or store is
-  // in the WB stage). The branch or jump speculatively begins the fetch but is held back from completing
+  // in the WB stage). The branch or jump speculatively begins the fetch but is held back from
-  // until it is certain the outstanding access hasn't seen a memory error. This logic ensures only
+  // completing until it is certain the outstanding access hasn't seen a memory error. This logic
-  // the first cycle of a branch or jump set is sent to the controller to prevent needless extra IF
+  // ensures only the first cycle of a branch or jump set is sent to the controller to prevent
-  // flushes and fetches.
+  // needless extra IF flushes and fetches.
   assign jump_set        = jump_set_raw        & ~branch_jump_set_done_q;
   assign branch_set      = branch_set_raw      & ~branch_jump_set_done_q;
   assign branch_set_spec = branch_set_raw_spec & ~branch_jump_set_done_q;
@@ -716,7 +719,8 @@ module ibex_id_stage #(
 
   end else begin : g_nosec_branch_taken
 
-    // Signal unused without fixed time execution mode - only taken branches will trigger branch_set_raw
+    // Signal unused without fixed time execution mode - only taken branches will trigger
+    // branch_set_raw
     assign branch_taken = 1'b1;
 
   end

rtl/ibex_multdiv_fast.sv

@@ -224,7 +224,7 @@ module ibex_multdiv_fast #(
 
           summand1 = '0;
           summand2 = accum;
-          summand3 = mult3_res;
+          summand3 = $unsigned(mult3_res);
 
           mult_state_d = MULL;
           mult_valid = 1'b1;