Fix waveform/coverage dump mode (#215)

dv/uvm/Makefile

@@ -93,7 +93,7 @@ compile:
      ${COMMON_OPTS} \
      --simulator=${SIMULATOR} \
      --en_cov=${COV} \
-     --en_wave=${WAVE} \
+     --en_wave=${WAVES} \
 
 # Run ibex RTL simulation with random instructions
 rtl_sim:
@@ -104,7 +104,7 @@ rtl_sim:
      ${COMMON_OPTS} \
      --simulator=${SIMULATOR} \
      --en_cov=${COV} \
-     --en_wave=${WAVE} \
+     --en_wave=${WAVES} \
      ${SIM_OPTS}
 
 # Compare the regression result between ISS and RTL sim

dv/uvm/sim.py

@@ -159,6 +159,7 @@ def rtl_sim(sim_cmd, test_list, output_dir, bin_dir, lsf_cmd, seed, opts, verbos
   # Run the RTL simulation
   sim_cmd = re.sub("<out>", output_dir, sim_cmd)
   sim_cmd = re.sub("<sim_opts>", opts, sim_cmd)
+  sim_cmd = re.sub("<cwd>", cwd, sim_cmd)
   print ("Running RTL simulation...")
   cmd_list = []
   for test in test_list:

dv/uvm/yaml/rtl_simulation.yaml

@@ -22,8 +22,7 @@
          -Mdir=<out>/vcs_simv.csrc
          -o <out>/vcs_simv
          -debug_access+pp
-         -lca -kdb
-         <wave_opts> <cov_opts>"
+         -lca -kdb <wave_opts> <cov_opts>"
     cov_opts: >
       -cm line+tgl+assert+fsm+branch
       -cm_tgl portsonly
@@ -36,7 +35,7 @@
       -debug_access+all -ucli -do vcs.tcl
   sim:
     cmd: >
-      <out>/vcs_simv +vcs+lic+wait <sim_opts>
+      <out>/vcs_simv +vcs+lic+wait <sim_opts> <wave_opts> <cov_opts>
     cov_opts: >
       -cm line+tgl+assert+fsm+branch
       -cm_dir <out>/test.vdb
@@ -44,4 +43,4 @@
       -assert nopostproc
       -cm_name test_<seed>
     wave_opts: >
-      -ucli -do vcs.tcl
+      -ucli -do <cwd>/vcs.tcl