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Enable WFI test in regression (#190)

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taoliug 2019-07-24 13:52:00 -07:00 • committed by GitHub
parent 2bf1ab923a
commit 511b205226
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4 changed files with 13 additions and 7 deletions
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3
dv/uvm/common/irq_agent/irq_master_driver.sv
View file

@ -47,9 +47,6 @@ class irq_master_driver extends uvm_driver #(irq_seq_item);
endtask : reset_signals endtask : reset_signals
virtual protected task drive_seq_item (irq_seq_item trans); virtual protected task drive_seq_item (irq_seq_item trans);
if (trans.delay > 0) begin
repeat(trans.delay) @(posedge vif.clock);
end
vif.irq_software <= trans.irq_software; vif.irq_software <= trans.irq_software;
vif.irq_timer <= trans.irq_timer; vif.irq_timer <= trans.irq_timer;
vif.irq_external <= trans.irq_external; vif.irq_external <= trans.irq_external;

12
dv/uvm/common/irq_agent/irq_seq_item.sv
View file

@ -9,7 +9,16 @@ class irq_seq_item extends uvm_sequence_item;
rand bit irq_external; rand bit irq_external;
rand bit [14:0] irq_fast; rand bit [14:0] irq_fast;
rand bit irq_nm; rand bit irq_nm;
rand int unsigned delay; rand int num_of_interrupt;
constraint num_of_interrupt_c {
num_of_interrupt inside {[1:19]};
$countones({irq_software, irq_timer, irq_external, irq_fast, irq_nm}) == num_of_interrupt;
}
constraint bring_up_c {
soft num_of_interrupt == 1;
}
`uvm_object_utils_begin(irq_seq_item) `uvm_object_utils_begin(irq_seq_item)
`uvm_field_int(irq_software, UVM_DEFAULT) `uvm_field_int(irq_software, UVM_DEFAULT)
@ -17,7 +26,6 @@ class irq_seq_item extends uvm_sequence_item;
`uvm_field_int(irq_external, UVM_DEFAULT) `uvm_field_int(irq_external, UVM_DEFAULT)
`uvm_field_int(irq_fast, UVM_DEFAULT) `uvm_field_int(irq_fast, UVM_DEFAULT)
`uvm_field_int(irq_nm, UVM_DEFAULT) `uvm_field_int(irq_nm, UVM_DEFAULT)
`uvm_field_int(delay, UVM_DEFAULT)
`uvm_object_utils_end `uvm_object_utils_end
`uvm_object_new `uvm_object_new

3
dv/uvm/riscv_dv_extension/ibex_core_setting.sv
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@ -94,6 +94,7 @@ privileged_reg_t implemented_csr[$] = {
MTVEC, // Machine trap-handler base address MTVEC, // Machine trap-handler base address
MEPC, // Machine exception program counter MEPC, // Machine exception program counter
MCAUSE, // Machine trap cause MCAUSE, // Machine trap cause
MTVAL // Machine bad address or instruction MTVAL, // Machine bad address or instruction
MIE // Machine interrupt enable
// TODO: Add performance CSRs and debug mode CSR // TODO: Add performance CSRs and debug mode CSR
}; };

2
dv/uvm/riscv_dv_extension/testlist
View file

@ -17,5 +17,5 @@ riscv_sfence_exception_test : 0 :
riscv_illegal_instr_test : 10 : riscv_illegal_instr_test : 10 :
riscv_hint_instr_test : 10 : riscv_hint_instr_test : 10 :
riscv_ebreak_test : 20 : riscv_ebreak_test : 20 :
riscv_wfi_test : 0 : riscv_wfi_test : 5 : +enable_interrupt=1
//-------------------------------------------------------------------- //--------------------------------------------------------------------