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Merge pull request #16 from MikeOpenHWGroup/main

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Working manifest (temporary solution for simulation)
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Mike Thompson 2022-10-14 13:33:40 -04:00 • committed by GitHub
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///////////////////////////////////////////////////////////////////////////////
//
// Copyright 2022 OpenHW Group
//
// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// https://solderpad.org/licenses/
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
///////////////////////////////////////////////////////////////////////////////
//
// Manifest for the CV32E20 RTL model.
// - Format based on manifest used by other CORE-V cores.
// - Intended to be used by both synthesis and simulation.
// - Relevent synthesis and simulation scripts/Makefiles must set the shell
// ENV variable DESIGN_RTL_DIR as required.
//
// TODO: Replace once-and-for-all with unified manifest (FuseSoc?)
//
///////////////////////////////////////////////////////////////////////////////
+incdir+${DESIGN_RTL_DIR}/../shared/rtl/
+incdir+${DESIGN_RTL_DIR}/../rtl
+incdir+${DESIGN_RTL_DIR}/../shared/rtl/sim
+incdir+${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/ip/prim/rtl
+incdir+${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/dv/sv/dv_utils
${DESIGN_RTL_DIR}/ibex_pkg.sv
${DESIGN_RTL_DIR}/ibex_tracer_pkg.sv
${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/ip/prim/rtl/prim_secded_pkg.sv
${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_pkg.sv
${DESIGN_RTL_DIR}/ibex_alu.sv
${DESIGN_RTL_DIR}/ibex_branch_predict.sv
${DESIGN_RTL_DIR}/ibex_compressed_decoder.sv
${DESIGN_RTL_DIR}/ibex_controller.sv
${DESIGN_RTL_DIR}/ibex_cs_registers.sv
${DESIGN_RTL_DIR}/ibex_csr.sv
${DESIGN_RTL_DIR}/ibex_counter.sv
${DESIGN_RTL_DIR}/ibex_decoder.sv
${DESIGN_RTL_DIR}/ibex_ex_block.sv
${DESIGN_RTL_DIR}/ibex_fetch_fifo.sv
${DESIGN_RTL_DIR}/ibex_id_stage.sv
${DESIGN_RTL_DIR}/ibex_if_stage.sv
${DESIGN_RTL_DIR}/ibex_load_store_unit.sv
${DESIGN_RTL_DIR}/ibex_multdiv_fast.sv
${DESIGN_RTL_DIR}/ibex_multdiv_slow.sv
${DESIGN_RTL_DIR}/ibex_prefetch_buffer.sv
${DESIGN_RTL_DIR}/ibex_pmp.sv
${DESIGN_RTL_DIR}/ibex_register_file_ff.sv
${DESIGN_RTL_DIR}/ibex_wb_stage.sv
${DESIGN_RTL_DIR}/ibex_dummy_instr.sv
${DESIGN_RTL_DIR}/ibex_core.sv
${DESIGN_RTL_DIR}/ibex_top.sv
${DESIGN_RTL_DIR}/ibex_top_tracing.sv
${DESIGN_RTL_DIR}/ibex_tracer.sv
${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_buf.sv
${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_gating.sv
${DESIGN_RTL_DIR}/../dv/uvm/core_ibex/common/prim/prim_pkg.sv
${DESIGN_RTL_DIR}/../dv/uvm/core_ibex/common/prim/prim_clock_gating.sv
${DESIGN_RTL_DIR}/../dv/uvm/core_ibex/common/prim/prim_buf.sv