Change size of core and cluster id

cs_registers.sv

@@ -43,8 +43,8 @@ module riscv_cs_registers
   input  logic        rst_n,
 
   // Core and Cluster ID
-  input  logic  [4:0] core_id_i,
-  input  logic  [4:0] cluster_id_i,
+  input  logic  [3:0] core_id_i,
+  input  logic  [5:0] cluster_id_i,
 
   // Interface to registers (SRAM like)
   input  logic        csr_access_i,
@@ -158,7 +158,7 @@ module riscv_cs_registers
       // mimpid: PULP, anonymous source (no allocated ID yet)
       12'hF01: csr_rdata_int = 32'h00_00_80_00;
       // mhartid: unique hardware thread id
-      12'hF10: csr_rdata_int = {22'b0, cluster_id_i, core_id_i};
+      12'hF10: csr_rdata_int = {21'b0, cluster_id_i[5:0], 1'b0, core_id_i[3:0]};
 
       // hardware loops
       12'h7B0: csr_rdata_int = hwlp_start_i[0];

debug_unit.sv

@@ -396,18 +396,6 @@ module riscv_debug_unit
     end
   end
 
-  //----------------------------------------------------------------------------
-  // rvalid generation
-  //----------------------------------------------------------------------------
-  always_ff @(posedge clk, negedge rst_n)
-  begin
-    if (~rst_n) begin
-      debug_rvalid_o <= 1'b0;
-    end else begin
-      debug_rvalid_o <= debug_gnt_o; // always give the rvalid one cycle after gnt
-    end
-  end
-
   //----------------------------------------------------------------------------
   // NPC/PPC selection
   //----------------------------------------------------------------------------

riscv_core.sv

@@ -42,8 +42,8 @@ module riscv_core
 
   // Core ID, Cluster ID and boot address are considered more or less static
   input  logic [31:0] boot_addr_i,
-  input  logic [4:0]  core_id_i,
-  input  logic [4:0]  cluster_id_i,
+  input  logic [ 3:0]  core_id_i,
+  input  logic [ 5:0]  cluster_id_i,
 
   // Instruction memory interface
   output logic                         instr_req_o,