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Fix some smallish issues

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This commit is contained in:
Andreas Traber 2016-04-20 14:17:09 +02:00
parent 5e30493243
commit 57b77ba394
2 changed files with 6 additions and 5 deletions
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9
debug_unit.sv
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@ -130,7 +130,7 @@ module riscv_debug_unit
// CSR access
if (state_q == FIRST) begin
// only grant in second cycle, address and data have been latched by then
debug_gnt_o = 1'b1; // grant it even when invalid access to not block
debug_gnt_o = 1'b0;
state_n = SECOND;
if (debug_halted_o) begin
@ -138,6 +138,7 @@ module riscv_debug_unit
csr_req_n = 1'b1;
end
end else begin
debug_gnt_o = 1'b1; // grant it even when invalid access to not block
state_n = FIRST;
csr_we_o = 1'b1;
end
@ -198,7 +199,7 @@ module riscv_debug_unit
end
end
default:;
default: debug_gnt_o = 1'b1; // grant it even when invalid access to not block
endcase
end
end else begin
@ -240,7 +241,7 @@ module riscv_debug_unit
end
end
default:;
default: debug_gnt_o = 1'b1; // grant it even when invalid access to not block
endcase
end
end
@ -463,7 +464,7 @@ module riscv_debug_unit
if (debug_req_i) begin
addr_q <= debug_addr_i;
wdata_q <= debug_wdata_i;
state_q <= FIRST;
state_q <= state_n;
end
if (debug_req_i | debug_rvalid_o) begin

2
exc_controller.sv
View file

@ -114,7 +114,7 @@ module riscv_exc_controller
end
end
if (ecall_insn_i) begin
if (ecall_insn_i & (~dbg_settings_i[`DBG_SETS_ECALL])) begin
cause_int = 6'b0_01000;
pc_mux_int = `EXC_PC_ECALL;
end