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[syn] Synthesis fixes
Correcting some small issues that cause newer versions of OpenSTA to fail (previously it issued an error and continued). - ABC/OpenSTA disagree how set_driving_cell command works so introduce seperate ABC SDC file - Run clean before generating STA netlist, otherwise yosys generates some assignements to unused wires that OpenSTA's verilog parser dislikes
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4 changed files with 10 additions and 3 deletions
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@ -2,5 +2,5 @@
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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set_driving_cell BUF_X2
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set_driving_cell [all_inputs] -lib_cell BUF_X2
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set_load 10.0 [all_outputs]
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6
syn/ibex_core_abc.nangate.sdc
Normal file
6
syn/ibex_core_abc.nangate.sdc
Normal file
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@ -0,0 +1,6 @@
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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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set_driving_cell BUF_X2
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set_load 10.0 [all_outputs]
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@ -21,6 +21,7 @@ if { $lr_synth_timing_run } {
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set_flow_var cell_library_name "nangate" "Name of cell library"
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#set_flow_var sdc_file "${top_module}.sdc" "SDC file"
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set_flow_var sdc_file_in "${lr_synth_top_module}.${lr_synth_cell_library_name}.sdc" "Input SDC file"
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set_flow_var abc_sdc_file_in "${lr_synth_top_module}_abc.${lr_synth_cell_library_name}.sdc" "Input SDC file for ABC"
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set flop_in_pin_default "*/D"
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set flop_out_pin_default "*/Q"
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@ -31,7 +31,7 @@ yosys "opt"
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set yosys_abc_clk_period [expr $lr_synth_clk_period - $lr_synth_abc_clk_uprate]
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if { $lr_synth_timing_run } {
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yosys "abc -liberty $lr_synth_cell_library_path -constr $lr_synth_sdc_file_out -D $yosys_abc_clk_period"
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yosys "abc -liberty $lr_synth_cell_library_path -constr $lr_synth_abc_sdc_file_in -D $yosys_abc_clk_period"
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} else {
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yosys "abc -liberty $lr_synth_cell_library_path"
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}
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@ -43,7 +43,7 @@ if { $lr_synth_timing_run } {
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# Produce netlist that OpenSTA can use
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yosys "setundef -zero"
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yosys "splitnets"
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yosys "clean"
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yosys "write_verilog -noattr -noexpr -nohex -nodec $lr_synth_sta_netlist_out"
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}
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