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[rtl] Instantiate shadow CSRs
Instantiate shadow CSRs and wire up to the alert output. Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
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Tom Roberts
Tom Roberts
parent
c1cfb2106e
commit
5826af8ad9
3 changed files with 35 additions and 11 deletions
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@ -69,3 +69,10 @@ This adds a check that the PC driven from the IF stage has not been modified.
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A check is asserted that the current IF stage PC equals the previous PC plus the correct increment.
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The check is disabled after branches and after reset.
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If a mismatch is detected, a major alert is signaled.
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Shadow CSRs
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-----------
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Certain critical CSRs (`mstatus`, `mtvec`, `cpuctrl`, `pmpcfg` and `pmpaddr`) have extra glitch detection enabled.
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This creates a second copy of the register which stores a complemented version of the main CSR data.
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A constant check is made that the two copies are consistent, and a major alert is signalled if not.
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@ -113,6 +113,7 @@ module ibex_core #(
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localparam bit DataIndTiming = SecureIbex;
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localparam bit DummyInstructions = SecureIbex;
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localparam bit PCIncrCheck = SecureIbex;
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localparam bit ShadowCSR = SecureIbex;
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// Speculative branch option, trades-off performance against timing.
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// Setting this to 1 eases branch target critical paths significantly but reduces performance
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// by ~3% (based on CoreMark/MHz score).
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@ -149,6 +150,7 @@ module ibex_core #(
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logic icache_enable;
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logic icache_inval;
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logic pc_mismatch_alert;
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logic csr_shadow_err;
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logic instr_first_cycle_id;
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logic instr_valid_clear;
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@ -892,7 +894,7 @@ module ibex_core #(
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assign alert_minor_o = 1'b0;
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// Major alert - core is unrecoverable
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assign alert_major_o = rf_ecc_err_comb | pc_mismatch_alert;
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assign alert_major_o = rf_ecc_err_comb | pc_mismatch_alert | csr_shadow_err;
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`ASSERT_KNOWN(IbexAlertMinorX, alert_minor_o)
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`ASSERT_KNOWN(IbexAlertMajorX, alert_major_o)
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@ -958,6 +960,7 @@ module ibex_core #(
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.DbgHwBreakNum ( DbgHwBreakNum ),
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.DataIndTiming ( DataIndTiming ),
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.DummyInstructions ( DummyInstructions ),
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.ShadowCSR ( ShadowCSR ),
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.ICache ( ICache ),
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.MHPMCounterNum ( MHPMCounterNum ),
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.MHPMCounterWidth ( MHPMCounterWidth ),
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@ -1025,6 +1028,7 @@ module ibex_core #(
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.dummy_instr_seed_en_o ( dummy_instr_seed_en ),
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.dummy_instr_seed_o ( dummy_instr_seed ),
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.icache_enable_o ( icache_enable ),
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.csr_shadow_err_o ( csr_shadow_err ),
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.csr_save_if_i ( csr_save_if ),
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.csr_save_id_i ( csr_save_id ),
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@ -17,6 +17,7 @@ module ibex_cs_registers #(
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parameter int unsigned DbgHwBreakNum = 1,
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parameter bit DataIndTiming = 1'b0,
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parameter bit DummyInstructions = 1'b0,
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parameter bit ShadowCSR = 1'b0,
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parameter bit ICache = 1'b0,
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parameter int unsigned MHPMCounterNum = 10,
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parameter int unsigned MHPMCounterWidth = 40,
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@ -88,6 +89,7 @@ module ibex_cs_registers #(
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output logic dummy_instr_seed_en_o,
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output logic [31:0] dummy_instr_seed_o,
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output logic icache_enable_o,
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output logic csr_shadow_err_o,
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// Exception save/restore
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input logic csr_save_if_i,
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@ -179,6 +181,7 @@ module ibex_cs_registers #(
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// CSRs
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priv_lvl_e priv_lvl_q, priv_lvl_d;
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status_t mstatus_q, mstatus_d;
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logic mstatus_err;
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logic mstatus_en;
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irqs_t mie_q, mie_d;
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logic mie_en;
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@ -191,6 +194,7 @@ module ibex_cs_registers #(
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logic [31:0] mtval_q, mtval_d;
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logic mtval_en;
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logic [31:0] mtvec_q, mtvec_d;
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logic mtvec_err;
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logic mtvec_en;
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irqs_t mip;
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dcsr_t dcsr_q, dcsr_d;
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@ -211,6 +215,7 @@ module ibex_cs_registers #(
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// PMP Signals
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logic [31:0] pmp_addr_rdata [PMP_MAX_REGIONS];
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logic [PMP_CFG_W-1:0] pmp_cfg_rdata [PMP_MAX_REGIONS];
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logic pmp_csr_err;
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// Hardware performance monitor signals
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logic [31:0] mcountinhibit;
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@ -239,6 +244,7 @@ module ibex_cs_registers #(
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// CPU control bits
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cpu_ctrl_t cpuctrl_q, cpuctrl_d, cpuctrl_wdata;
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logic cpuctrl_we;
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logic cpuctrl_err;
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// CSR update logic
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logic [31:0] csr_wdata_int;
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@ -734,7 +740,7 @@ module ibex_cs_registers #(
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tw: 1'b0};
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ibex_csr #(
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.Width ($bits(status_t)),
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.ShadowCopy (1'b0),
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.ShadowCopy (ShadowCSR),
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.ResetValue ({MSTATUS_RST_VAL})
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) u_mstatus_csr (
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.clk_i (clk_i),
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@ -742,7 +748,7 @@ module ibex_cs_registers #(
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.wr_data_i ({mstatus_d}),
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.wr_en_i (mstatus_en),
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.rd_data_o (mstatus_q),
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.rd_error_o ()
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.rd_error_o (mstatus_err)
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);
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// MEPC
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@ -822,7 +828,7 @@ module ibex_cs_registers #(
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// MTVEC
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ibex_csr #(
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.Width (32),
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.ShadowCopy (1'b0),
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.ShadowCopy (ShadowCSR),
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.ResetValue (32'd1)
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) u_mtvec_csr (
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.clk_i (clk_i),
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@ -830,7 +836,7 @@ module ibex_cs_registers #(
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.wr_data_i (mtvec_d),
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.wr_en_i (mtvec_en),
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.rd_data_o (mtvec_q),
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.rd_error_o ()
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.rd_error_o (mtvec_err)
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);
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// DCSR
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@ -950,7 +956,9 @@ module ibex_cs_registers #(
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pmp_cfg_t pmp_cfg_wdata [PMPNumRegions];
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logic [31:0] pmp_addr [PMPNumRegions];
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logic [PMPNumRegions-1:0] pmp_cfg_we;
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logic [PMPNumRegions-1:0] pmp_cfg_err;
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logic [PMPNumRegions-1:0] pmp_addr_we;
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logic [PMPNumRegions-1:0] pmp_addr_err;
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// Expanded / qualified register read data
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for (genvar i = 0; i < PMP_MAX_REGIONS; i++) begin : g_exp_rd_data
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@ -1023,7 +1031,7 @@ module ibex_cs_registers #(
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ibex_csr #(
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.Width ($bits(pmp_cfg_t)),
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.ShadowCopy (1'b0),
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.ShadowCopy (ShadowCSR),
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.ResetValue ('0)
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) u_pmp_cfg_csr (
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.clk_i (clk_i),
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@ -1031,7 +1039,7 @@ module ibex_cs_registers #(
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.wr_data_i ({pmp_cfg_wdata[i]}),
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.wr_en_i (pmp_cfg_we[i]),
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.rd_data_o (pmp_cfg[i]),
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.rd_error_o ()
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.rd_error_o (pmp_cfg_err[i])
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);
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// --------------------------
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@ -1048,7 +1056,7 @@ module ibex_cs_registers #(
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ibex_csr #(
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.Width (32),
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.ShadowCopy (1'b0),
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.ShadowCopy (ShadowCSR),
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.ResetValue ('0)
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) u_pmp_addr_csr (
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.clk_i (clk_i),
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@ -1056,13 +1064,15 @@ module ibex_cs_registers #(
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.wr_data_i (csr_wdata_int),
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.wr_en_i (pmp_addr_we[i]),
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.rd_data_o (pmp_addr[i]),
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.rd_error_o ()
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.rd_error_o (pmp_addr_err[i])
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);
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assign csr_pmp_cfg_o[i] = pmp_cfg[i];
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assign csr_pmp_addr_o[i] = {pmp_addr[i],2'b00};
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end
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assign pmp_csr_err = (|pmp_cfg_err) | (|pmp_addr_err);
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end else begin : g_no_pmp_tieoffs
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// Generate tieoffs when PMP is not configured
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for (genvar i = 0; i < PMP_MAX_REGIONS; i++) begin : g_rdata
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@ -1073,6 +1083,7 @@ module ibex_cs_registers #(
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assign csr_pmp_cfg_o[i] = pmp_cfg_t'(1'b0);
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assign csr_pmp_addr_o[i] = '0;
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end
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assign pmp_csr_err = 1'b0;
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end
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//////////////////////////
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@ -1387,7 +1398,7 @@ module ibex_cs_registers #(
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ibex_csr #(
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.Width ($bits(cpu_ctrl_t)),
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.ShadowCopy (1'b0),
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.ShadowCopy (ShadowCSR),
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.ResetValue ('0)
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) u_cpuctrl_csr (
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.clk_i (clk_i),
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@ -1395,9 +1406,11 @@ module ibex_cs_registers #(
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.wr_data_i ({cpuctrl_d}),
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.wr_en_i (cpuctrl_we),
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.rd_data_o (cpuctrl_q),
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.rd_error_o ()
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.rd_error_o (cpuctrl_err)
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);
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assign csr_shadow_err_o = mstatus_err | mtvec_err | pmp_csr_err | cpuctrl_err;
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////////////////
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// Assertions //
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////////////////
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