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https://github.com/openhwgroup/cve2.git
synced 2025-04-24 05:57:28 -04:00
fixed NCSIM simulation issue related to riscv_tracer
This commit is contained in:
Gautschi
parent
25a7705051
commit
59708f4422
1 changed files with 61 additions and 61 deletions
122
riscv_tracer.sv
122
riscv_tracer.sv
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@ -159,89 +159,89 @@ module riscv_tracer
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function void printRInstr(input string mnemonic);
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begin
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regs_read.push_back({>> {rs1, rs1_value}});
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regs_read.push_back({>> {rs2, rs2_value}});
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regs_write.push_back({>> {rd, 'x}});
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regs_read.push_back('{rs1, rs1_value});
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regs_read.push_back('{rs2, rs2_value});
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regs_write.push_back('{rd, 'x});
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str = $sformatf("%-16s x%0d, x%0d, x%0d", mnemonic, rd, rs1, rs2);
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end
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endfunction // printRInstr
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function void printAddNInstr(input string mnemonic);
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begin
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regs_read.push_back({>> {rs1, rs1_value}});
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regs_read.push_back({>> {rs2, rs2_value}});
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regs_write.push_back({>> {rd, 'x}});
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regs_read.push_back('{rs1, rs1_value});
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regs_read.push_back('{rs2, rs2_value});
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regs_write.push_back('{rd, 'x});
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str = $sformatf("%-16s x%0d, x%0d, x%0d, 0x%0d", mnemonic, rd, rs1, rs2, $unsigned(imm_s3_type[4:0]));
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end
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endfunction // printAddNInstr
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function void printR1Instr(input string mnemonic);
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begin
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regs_read.push_back({>> {rs1, rs1_value}});
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regs_write.push_back({>> {rd, 'x}});
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regs_read.push_back('{rs1, rs1_value});
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regs_write.push_back('{rd, 'x});
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str = $sformatf("%-16s x%0d, x%0d", mnemonic, rd, rs1);
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end
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endfunction // printR1Instr
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function void printR3Instr(input string mnemonic);
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begin
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regs_read.push_back({>> {rd, rs3_value}});
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regs_read.push_back({>> {rs1, rs1_value}});
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regs_read.push_back({>> {rs2, rs2_value}});
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regs_write.push_back({>> {rd, 'x}});
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regs_read.push_back('{rd, rs3_value});
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regs_read.push_back('{rs1, rs1_value});
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regs_read.push_back('{rs2, rs2_value});
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regs_write.push_back('{rd, 'x});
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str = $sformatf("%-16s x%0d, x%0d, x%0d", mnemonic, rd, rs1, rs2);
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end
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endfunction // printR3Instr
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function void printClipInstr(input string mnemonic);
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begin
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regs_read.push_back({>> {rs1, rs1_value}});
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regs_write.push_back({>> {rd, 'x}});
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regs_read.push_back('{rs1, rs1_value});
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regs_write.push_back('{rd, 'x});
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str = $sformatf("%-16s x%0d, x%0d, %0d", mnemonic, rd, rs1, $unsigned(imm_clip_type));
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end
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endfunction // printRInstr
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function void printIInstr(input string mnemonic);
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begin
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regs_read.push_back({>> {rs1, rs1_value}});
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regs_write.push_back({>> {rd, 'x}});
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regs_read.push_back('{rs1, rs1_value});
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regs_write.push_back('{rd, 'x});
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str = $sformatf("%-16s x%0d, x%0d, %0d", mnemonic, rd, rs1, $signed(imm_i_type));
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end
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endfunction // printIInstr
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function void printIuInstr(input string mnemonic);
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begin
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regs_read.push_back({>> {rs1, rs1_value}});
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regs_write.push_back({>> {rd, 'x}});
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regs_read.push_back('{rs1, rs1_value});
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regs_write.push_back('{rd, 'x});
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str = $sformatf("%-16s x%0d, x%0d, 0x%0x", mnemonic, rd, rs1, imm_i_type);
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end
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endfunction // printIuInstr
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function void printUInstr(input string mnemonic);
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begin
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regs_write.push_back({>> {rd, 'x}});
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regs_write.push_back('{rd, 'x});
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str = $sformatf("%-16s x%0d, 0x%0h", mnemonic, rd, {imm_u_type[31:12], 12'h000});
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end
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endfunction // printUInstr
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function void printUJInstr(input string mnemonic);
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begin
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regs_write.push_back({>> {rd, 'x}});
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regs_write.push_back('{rd, 'x});
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str = $sformatf("%-16s x%0d, %0d", mnemonic, rd, $signed(imm_uj_type));
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end
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endfunction // printUJInstr
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function void printSBInstr(input string mnemonic);
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begin
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regs_read.push_back({>> {rs1, rs1_value}});
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regs_read.push_back({>> {rs2, rs2_value}});
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regs_read.push_back('{rs1, rs1_value});
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regs_read.push_back('{rs2, rs2_value});
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str = $sformatf("%-16s x%0d, x%0d, %0d", mnemonic, rs1, rs2, $signed(imm_sb_type));
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end
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endfunction // printSBInstr
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function void printSBallInstr(input string mnemonic);
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begin
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regs_read.push_back({>> {rs1, rs1_value}});
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regs_read.push_back('{rs1, rs1_value});
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str = $sformatf("%-16s x%0d, %0d", mnemonic, rs1, $signed(imm_sb_type));
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end
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endfunction // printSBInstr
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@ -251,10 +251,10 @@ module riscv_tracer
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begin
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csr = instr[31:20];
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regs_write.push_back({>> {rd, 'x}});
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regs_write.push_back('{rd, 'x});
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if (instr[14] == 1'b0) begin
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regs_read.push_back({>> {rs1, rs1_value}});
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regs_read.push_back('{rs1, rs1_value});
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str = $sformatf("%-16s x%0d, x%0d, 0x%h", mnemonic, rd, rs1, csr);
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end else begin
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str = $sformatf("%-16s x%0d, 0x%h, 0x%h", mnemonic, rd, imm_z_type, csr);
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@ -264,17 +264,17 @@ module riscv_tracer
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function void printBit1Instr(input string mnemonic);
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begin
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regs_read.push_back({>> {rs1, rs1_value}});
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regs_write.push_back({>> {rd, 'x}});
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regs_read.push_back('{rs1, rs1_value});
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regs_write.push_back('{rd, 'x});
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str = $sformatf("%-16s x%0d, x%0d, %0d, %0d", mnemonic, rd, rs1, imm_s3_type, imm_s2_type);
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end
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endfunction
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function void printBit2Instr(input string mnemonic);
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begin
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regs_read.push_back({>> {rd, rs3_value}});
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regs_read.push_back({>> {rs1, rs1_value}});
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regs_write.push_back({>> {rd, 'x}});
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regs_read.push_back('{rd, rs3_value});
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regs_read.push_back('{rs1, rs1_value});
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regs_write.push_back('{rd, 'x});
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str = $sformatf("%-16s x%0d, x%0d, %0d, %0d", mnemonic, rd, rs1, imm_s3_type, imm_s2_type);
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end
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endfunction
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@ -302,28 +302,28 @@ module riscv_tracer
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end
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endcase
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regs_write.push_back({>> {rd, 'x}});
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regs_write.push_back('{rd, 'x});
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if (instr[14:12] != 3'b111) begin
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// regular load
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if (instr[6:0] != `OPCODE_LOAD_POST) begin
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regs_read.push_back({>> {rs1, rs1_value}});
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regs_read.push_back('{rs1, rs1_value});
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str = $sformatf("%-16s x%0d, %0d(x%0d)", mnemonic, rd, $signed(imm_i_type), rs1);
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end else begin
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regs_read.push_back({>> {rs1, rs1_value}});
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regs_write.push_back({>> {rs1, 'x}});
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regs_read.push_back('{rs1, rs1_value});
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regs_write.push_back('{rs1, 'x});
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str = $sformatf("p.%-14s x%0d, %0d(x%0d!)", mnemonic, rd, $signed(imm_i_type), rs1);
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end
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end else begin
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// reg-reg load
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if (instr[6:0] != `OPCODE_LOAD_POST) begin
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regs_read.push_back({>> {rs2, rs2_value}});
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regs_read.push_back({>> {rs1, rs1_value}});
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regs_read.push_back('{rs2, rs2_value});
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regs_read.push_back('{rs1, rs1_value});
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str = $sformatf("%-16s x%0d, x%0d(x%0d)", mnemonic, rd, rs2, rs1);
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end else begin
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regs_read.push_back({>> {rs2, rs2_value}});
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regs_read.push_back({>> {rs1, rs1_value}});
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regs_write.push_back({>> {rs1, 'x}});
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regs_read.push_back('{rs2, rs2_value});
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regs_read.push_back('{rs1, rs1_value});
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regs_write.push_back('{rs1, 'x});
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str = $sformatf("p.%-14s x%0d, x%0d(x%0d!)", mnemonic, rd, rs2, rs1);
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end
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end
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@ -347,27 +347,27 @@ module riscv_tracer
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if (instr[14] == 1'b0) begin
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// regular store
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if (instr[6:0] != `OPCODE_STORE_POST) begin
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regs_read.push_back({>> {rs2, rs2_value}});
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regs_read.push_back({>> {rs1, rs1_value}});
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regs_read.push_back('{rs2, rs2_value});
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regs_read.push_back('{rs1, rs1_value});
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str = $sformatf("%-16s x%0d, %0d(x%0d)", mnemonic, rs2, $signed(imm_s_type), rs1);
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end else begin
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regs_read.push_back({>> {rs2, rs2_value}});
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regs_read.push_back({>> {rs1, rs1_value}});
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regs_write.push_back({>> {rs1, 'x}});
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regs_read.push_back('{rs2, rs2_value});
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regs_read.push_back('{rs1, rs1_value});
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regs_write.push_back('{rs1, 'x});
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str = $sformatf("p.%-14s x%0d, %0d(x%0d!)", mnemonic, rs2, $signed(imm_s_type), rs1);
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end
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end else begin
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// reg-reg store
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if (instr[6:0] != `OPCODE_STORE_POST) begin
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regs_read.push_back({>> {rs2, rs2_value}});
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regs_read.push_back({>> {rs3, rs3_value}});
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regs_read.push_back({>> {rs1, rs1_value}});
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regs_read.push_back('{rs2, rs2_value});
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regs_read.push_back('{rs3, rs3_value});
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regs_read.push_back('{rs1, rs1_value});
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str = $sformatf("p.%-14s x%0d, x%0d(x%0d)", mnemonic, rs2, rs3, rs1);
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end else begin
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regs_read.push_back({>> {rs2, rs2_value}});
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regs_read.push_back({>> {rs3, rs3_value}});
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regs_read.push_back({>> {rs1, rs1_value}});
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regs_write.push_back({>> {rs1, 'x}});
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regs_read.push_back('{rs2, rs2_value});
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regs_read.push_back('{rs3, rs3_value});
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regs_read.push_back('{rs1, rs1_value});
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regs_write.push_back('{rs1, 'x});
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str = $sformatf("p.%-14s x%0d, x%0d(x%0d!)", mnemonic, rs2, rs3, rs1);
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end
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end
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@ -398,14 +398,14 @@ module riscv_tracer
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3'b001: str = $sformatf("%-16s 0x%0d, 0x%0h", mnemonic, rd, imm_iz_type);
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// lp.count
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3'b010: begin
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regs_read.push_back({>> {rs1, rs1_value}});
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regs_read.push_back('{rs1, rs1_value});
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str = $sformatf("%-16s 0x%0d, x%0d", mnemonic, rd, rs1);
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end
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// lp.counti
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3'b011: str = $sformatf("%-16s x%0d, 0x%0h", mnemonic, rd, imm_iz_type);
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// lp.setup
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3'b100: begin
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regs_read.push_back({>> {rs1, rs1_value}});
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regs_read.push_back('{rs1, rs1_value});
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str = $sformatf("%-16s 0x%0d, x%0d, 0x%0h", mnemonic, rd, rs1, imm_iz_type);
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end
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// lp.setupi
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@ -424,12 +424,12 @@ module riscv_tracer
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begin
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// always read rs1 and rs2 and write rd
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regs_read.push_back({>> {rs1, rs1_value}});
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regs_read.push_back({>> {rs2, rs2_value}});
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regs_write.push_back({>> {rd, 'x}});
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regs_read.push_back('{rs1, rs1_value});
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regs_read.push_back('{rs2, rs2_value});
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regs_write.push_back('{rd, 'x});
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if (instr[12])
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regs_read.push_back({>> {rd, rs3_value}});
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regs_read.push_back('{rd, rs3_value});
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case ({instr[31:30], instr[14]})
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3'b000: str_suf = "u";
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@ -469,8 +469,8 @@ module riscv_tracer
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begin
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// always read rs1 and write rd
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regs_read.push_back({>> {rs1, rs1_value}});
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regs_write.push_back({>> {rd, 'x}});
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regs_read.push_back('{rs1, rs1_value});
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regs_write.push_back('{rd, 'x});
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case (instr[14:13])
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2'b00: str_sci = "";
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@ -530,10 +530,10 @@ module riscv_tracer
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endcase
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if (str_sci == "") begin
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regs_read.push_back({>> {rs2, rs2_value}});
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regs_read.push_back('{rs2, rs2_value});
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str_args = $sformatf("x%0d, x%0d, x%0d", rd, rs1, rs2);
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end else if (str_sci == ".sc") begin
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regs_read.push_back({>> {rs2, rs2_value_vec}});
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regs_read.push_back('{rs2, rs2_value_vec});
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str_args = $sformatf("x%0d, x%0d, x%0d", rd, rs1, rs2);
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end else if (str_sci == ".sci") begin
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str_args = $sformatf("x%0d, x%0d, %s", rd, rs1, str_imm);
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