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[rtl] Fix jump signal stuck high during stall

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- Stalls due to preceding memory accesses in the WB stage shouldn't
  cause the jump signal to remain high.
- The jump signal being stuck high causes repeated memory accesses to
  the same address, and unnecessary stalling.
- Fixes lowRISC/opentitan#2099

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
This commit is contained in:
Tom Roberts 2020-05-01 15:52:56 +01:00 • committed by Tom Roberts
parent fd01562ff7
commit 5bcacb876d
1 changed files with 5 additions and 1 deletions
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6
rtl/ibex_id_stage.sv
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@ -193,6 +193,7 @@ module ibex_id_stage #(
logic branch_set, branch_set_d;
logic branch_taken;
logic jump_in_dec;
logic jump_set_dec;
logic jump_set;
logic instr_first_cycle;
@ -400,7 +401,7 @@ module ibex_id_stage #(
.dret_insn_o ( dret_insn_dec ),
.ecall_insn_o ( ecall_insn_dec ),
.wfi_insn_o ( wfi_insn_dec ),
.jump_set_o ( jump_set ),
.jump_set_o ( jump_set_dec ),
.branch_taken_i ( branch_taken ),
.icache_inval_o ( icache_inval_o ),
@ -663,6 +664,7 @@ module ibex_id_stage #(
// could generate needless prefetch buffer flushes and instruction fetches. ID/EX is designed such
// that this shouldn't ever happen.
`ASSERT(NeverDoubleBranch, branch_set |=> ~branch_set)
`ASSERT(NeverDoubleJump, jump_set |=> ~jump_set)
///////////////
// ID-EX FSM //
@ -692,6 +694,7 @@ module ibex_id_stage #(
stall_branch = 1'b0;
stall_alu = 1'b0;
branch_set_d = 1'b0;
jump_set = 1'b0;
perf_branch_o = 1'b0;
if (instr_executing) begin
@ -733,6 +736,7 @@ module ibex_id_stage #(
// BTALU means jumps only need one cycle
id_fsm_d = BranchTargetALU ? FIRST_CYCLE : MULTI_CYCLE;
stall_jump = ~BranchTargetALU;
jump_set = jump_set_dec;
end
alu_multicycle_dec: begin
stall_alu = 1'b1;