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Update google_riscv-dv to google/riscv-dv@74b8cb6 (#529)

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Update code from upstream repository https://github.com/google/riscv-
dv to revision 74b8cb65838f575d6e59e1c80a145d305fbca381

* fix ebreak generation in debug ROM (Udi Jonnalagadda)
* enable nested traps (Udi Jonnalagadda)

Signed-off-by: Udi <udij@google.com>
This commit is contained in:
udinator 2019-12-17 10:54:38 -08:00 • committed by GitHub
parent 7fef1b5afc
commit 5c07ced1e3
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GPG key ID: 4AEE18F83AFDEB23
4 changed files with 21 additions and 1 deletions
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2
vendor/google_riscv-dv.lock.hjson vendored
View file

@ -9,6 +9,6 @@
upstream:
{
url: https://github.com/google/riscv-dv
rev: 5b1dd4e2eb11d49d3275da80953efc0c50f90447
rev: 74b8cb65838f575d6e59e1c80a145d305fbca381
}
}

15
vendor/google_riscv-dv/src/riscv_asm_program_gen.sv vendored
View file

@ -802,6 +802,21 @@ class riscv_asm_program_gen extends uvm_object;
for (int i = 1; i < max_interrupt_vector_num; i++) begin
string intr_handler[$];
push_gpr_to_kernel_stack(status, scratch, cfg.mstatus_mprv, cfg.sp, cfg.tp, intr_handler);
// If nested interrupts are enabled, set xSTATUS.xIE in the interrupt handler
// to re-enable interrupt handling capabilities
if (cfg.enable_nested_interrupt) begin
case (status)
MSTATUS: begin
intr_handler.push_back($sformatf("csrsi 0x%0x, 0x%0x", status, 8));
end
SSTATUS: begin
intr_handler.push_back($sformatf("csrsi 0x%0x, 0x%0x", status, 2));
end
USTATUS: begin
intr_handler.push_back($sformatf("csrsi 0x%0x, 0x%0x", status, 1));
end
endcase
end
gen_signature_handshake(.instr(intr_handler), .signature_type(CORE_STATUS), .core_status(HANDLING_IRQ));
intr_handler = {intr_handler,
$sformatf("csrr x%0d, 0x%0x # %0s", cfg.gpr[0], cause, cause.name()),

2
vendor/google_riscv-dv/src/riscv_instr_gen_config.sv vendored
View file

@ -149,6 +149,7 @@ class riscv_instr_gen_config extends uvm_object;
string asm_test_suffix;
// Enable interrupt bit in MSTATUS (MIE, SIE, UIE)
bit enable_interrupt;
bit enable_nested_interrupt;
// We need a separate control knob for enabling timer interrupts, as Spike
// throws an exception if xIE.xTIE is enabled
bit enable_timer_irq;
@ -440,6 +441,7 @@ class riscv_instr_gen_config extends uvm_object;
get_int_arg_value("+num_of_tests=", num_of_tests);
get_int_arg_value("+enable_page_table_exception=", enable_page_table_exception);
get_bool_arg_value("+enable_interrupt=", enable_interrupt);
get_bool_arg_value("+enable_nested_interrupt=", enable_nested_interrupt);
get_bool_arg_value("+enable_timer_irq=", enable_timer_irq);
get_int_arg_value("+num_of_sub_program=", num_of_sub_program);
get_int_arg_value("+instr_cnt=", instr_cnt);

3
vendor/google_riscv-dv/src/riscv_instr_stream.sv vendored
View file

@ -221,6 +221,9 @@ class riscv_rand_instr_stream extends riscv_instr_stream;
((avail_regs.size() > 0) && !(SP inside {avail_regs}))) begin
exclude_instr = {C_ADDI4SPN, C_ADDI16SP, C_LWSP, C_LDSP};
end
if (is_in_debug && !cfg.enable_ebreak_in_debug_rom) begin
exclude_instr = {exclude_instr, EBREAK, C_EBREAK};
end
instr = riscv_instr::get_rand_instr(.include_instr(allowed_instr),
.exclude_instr(exclude_instr));
randomize_gpr(instr);