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Adding Reset-value and detailed table to MISA register in the CV32E20 UM

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AhmedEid0199 2025-01-14 04:29:42 +02:00
parent 370793f524
commit 5daea96181
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doc/03_reference/cs_registers.rst
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@ -140,9 +140,77 @@ Machine ISA Register (misa)
CSR Address: ``0x301``
Reset Value: ``0x4010_1104``
``misa`` is a WARL register which describes the ISA supported by the hart.
On Ibex, ``misa`` is hard-wired, i.e. it will remain unchanged after any write.
Detailed:
+-------------+------------+------------------------------------------------------------------------+
| **Bit #** | **Mode** | **Description** |
+=============+============+========================================================================+
| 31:30 | RO (0x01) | **MXL** (Machine XLEN) |
+-------------+------------+------------------------------------------------------------------------+
| 29:26 | RO (0x0) | (Reserved) |
+-------------+------------+------------------------------------------------------------------------+
| 25 | RO (0x0) | **Z** (Reserved) |
+-------------+------------+------------------------------------------------------------------------+
| 24 | RO (0x0) | **Y** (Reserved) |
+-------------+------------+------------------------------------------------------------------------+
| 23 | RO (0x0) | **X** (Non-standard extensions present) |
+-------------+------------+------------------------------------------------------------------------+
| 22 | RO (0x0) | **W** (Reserved) |
+-------------+------------+------------------------------------------------------------------------+
| 21 | RO (0x0) | **V** (Tentatively reserved for Vector extension) |
+-------------+------------+------------------------------------------------------------------------+
| 20 | RO (0x1) | **U** (User mode implemented) |
+-------------+------------+------------------------------------------------------------------------+
| 19 | RO (0x0) | **T** (Tentatively reserved for Transactional Memory extension) |
+-------------+------------+------------------------------------------------------------------------+
| 18 | RO (0x0) | **S** (Supervisor mode implemented) |
+-------------+------------+------------------------------------------------------------------------+
| 17 | RO (0x0) | **R** (Reserved) |
+-------------+------------+------------------------------------------------------------------------+
| 16 | RO (0x0) | **Q** (Quad-precision floating-point extension) |
+-------------+------------+------------------------------------------------------------------------+
| 15 | RO (0x0) | **P** (Tentatively reserved for Packed-SIMD extension) |
+-------------+------------+------------------------------------------------------------------------+
| 14 | RO (0x0) | **O** (Reserved) |
+-------------+------------+------------------------------------------------------------------------+
| 13 | RO (0x0) | **N** (User-level interrupts supported) |
+-------------+------------+------------------------------------------------------------------------+
| 12 | RO (0x1) | **M** (Integer Multiply/Divide extension) |
+-------------+------------+------------------------------------------------------------------------+
| 11 | RO (0x0) | **L** (Tentatively reserved for Decimal Floating-Point extension) |
+-------------+------------+------------------------------------------------------------------------+
| 10 | RO (0x0) | **K** (Reserved) |
+-------------+------------+------------------------------------------------------------------------+
| 9 | RO (0x0) | **J** (Tentatively reserved for Dynamically Translated Languages |
| | | extension) |
+-------------+------------+------------------------------------------------------------------------+
| 8 | RO (0x1) | **I** (RV32I/64I/128I base ISA) |
+-------------+------------+------------------------------------------------------------------------+
| 7 | RO (0x0) | **H** (Reserved) |
+-------------+------------+------------------------------------------------------------------------+
| 6 | RO (0x0) | **G** (Additional standard extensions present) |
+-------------+------------+------------------------------------------------------------------------+
| 5 | RO (0x0) | **F** (Single-precision floating-point extension) |
+-------------+------------+------------------------------------------------------------------------+
| 4 | RO (0x0) | **E** (RV32E base ISA) |
+-------------+------------+------------------------------------------------------------------------+
| 3 | RO (0x0) | **D** (Double-precision floating-point extension) |
+-------------+------------+------------------------------------------------------------------------+
| 2 | RO (0x1) | **C** (Compressed extension) |
+-------------+------------+------------------------------------------------------------------------+
| 1 | RO (0x0) | **B** (Tentatively reserved for Bit-Manipulation extension) |
+-------------+------------+------------------------------------------------------------------------+
| 0 | RO (0x0) | **A** (Atomic extension) |
+-------------+------------+------------------------------------------------------------------------+
* **B** = 0 if RV32B == RV32BNone and 1 otherwise, It's controlled by "RV32BEnabled" parameter
* **M** = 0 if RV32M == RV32MNone and 1 otherwise, It's controlled by "RV32MEnabled" parameter
* **MXL** = 1 (i.e. XLEN = 32)
Machine Interrupt Enable Register (mie)
---------------------------------------