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https://github.com/openhwgroup/cve2.git
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Adding Compressed Instruction support in tracer
Added compressed instruction decoder in the tracer to correctly trace compressed instructions with their mnemonics. Fixes #197
This commit is contained in:
Rahul Behl
Philipp Wagner
parent
1162b995fa
commit
60de915d6b
5 changed files with 215 additions and 11 deletions
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@ -56,15 +56,15 @@ lint_off -msg UNUSED -file "*/rtl/ibex_pmp.sv" -lines 16
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// Signal is not used: csr_pmp_addr
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// Signal not connected when PMP is not configured
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lint_off -msg UNUSED -file "*/rtl/ibex_core.sv" -lines 186
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lint_off -msg UNUSED -file "*/rtl/ibex_core.sv" -lines 185
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// Signal is not used: csr_pmp_cfg
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// Signal not connected when PMP is not configured
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lint_off -msg UNUSED -file "*/rtl/ibex_core.sv" -lines 187
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lint_off -msg UNUSED -file "*/rtl/ibex_core.sv" -lines 186
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// Signal is not used: priv_mode
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// Signal not connected when PMP is not configured
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lint_off -msg UNUSED -file "*/rtl/ibex_core.sv" -lines 199
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lint_off -msg UNUSED -file "*/rtl/ibex_core.sv" -lines 198
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// Signal unoptimizable: Feedback to clock or circular logic:
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// ibex_core.id_stage_i.controller_i.ctrl_fsm_cs
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@ -66,7 +66,6 @@ module ibex_core #(
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output logic rvfi_valid,
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output logic [63:0] rvfi_order,
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output logic [31:0] rvfi_insn,
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output logic [31:0] rvfi_insn_uncompressed,
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output logic rvfi_trap,
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output logic rvfi_halt,
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output logic rvfi_intr,
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@ -671,7 +670,6 @@ module ibex_core #(
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rvfi_intr <= '0;
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rvfi_order <= '0;
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rvfi_insn <= '0;
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rvfi_insn_uncompressed <= '0;
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rvfi_mode <= '0;
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rvfi_rs1_addr <= '0;
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rvfi_rs2_addr <= '0;
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@ -693,7 +691,6 @@ module ibex_core #(
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rvfi_intr <= rvfi_intr_d;
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rvfi_order <= rvfi_order + rvfi_valid;
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rvfi_insn <= rvfi_insn_id;
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rvfi_insn_uncompressed <= instr_rdata_id;
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rvfi_mode <= PRIV_LVL_M; // TODO: Update for user mode support
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rvfi_rs1_addr <= rvfi_rs1_addr_id;
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rvfi_rs2_addr <= rvfi_rs2_addr_id;
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@ -68,7 +68,6 @@ module ibex_core_tracing #(
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logic rvfi_valid;
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logic [63:0] rvfi_order;
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logic [31:0] rvfi_insn;
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logic [31:0] rvfi_insn_uncompressed;
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logic rvfi_trap;
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logic rvfi_halt;
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logic rvfi_intr;
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@ -131,7 +130,6 @@ module ibex_core_tracing #(
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.rvfi_valid,
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.rvfi_order,
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.rvfi_insn,
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.rvfi_insn_uncompressed,
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.rvfi_trap,
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.rvfi_halt,
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.rvfi_intr,
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@ -165,7 +163,7 @@ module ibex_core_tracing #(
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.valid_i ( rvfi_valid ),
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.pc_i ( rvfi_pc_rdata ),
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.instr_i ( rvfi_insn_uncompressed ),
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.instr_i ( rvfi_insn ),
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.rs1_value_i ( rvfi_rs1_rdata ),
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.rs2_value_i ( rvfi_rs2_rdata ),
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.ex_reg_addr_i ( rvfi_rd_addr ),
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@ -191,6 +191,131 @@ module ibex_tracer #(
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end
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endfunction // printCSRInstr
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function void printCRInstr(input string mnemonic);
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logic [4:0] rs1;
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logic [4:0] rs2;
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begin
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rs1 = instr_i[11:7];
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rs2 = instr_i[6:2];
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if (rs2 == 5'b0) begin
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regs_read.push_back('{rs1, rs1_value_i});
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str = $sformatf("%-16s x%0d", mnemonic, rs1);
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end else begin
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regs_write.push_back('{rs1, 'x});
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regs_read.push_back('{rs2, rs2_value_i});
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str = $sformatf("%-16s x%0d, x%0d", mnemonic, rs1, rs2);
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end
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end
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endfunction // printCRInstr
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function void printCIInstr(input string mnemonic);
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begin
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regs_write.push_back('{rd, 'x});
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str = $sformatf("%-16s x%0d, 0x%h", mnemonic, rd, {instr_i[12], instr_i[4:0]});
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end
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endfunction // printCIInstr
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function void printCIWInstr(input string mnemonic);
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logic [4:0] rd;
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begin
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rd = {2'b01, instr_i[4:2]};
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regs_write.push_back('{rd, 'x});
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str = $sformatf("%-16s x%0d, 0x%h", mnemonic, rd, {instr_i[10:7], instr_i[12:11], instr_i[5], instr_i[6]});
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end
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endfunction // printCIWInstr
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function void printCBInstr(input string mnemonic);
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logic [4:0] rs1;
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logic [8:1] imm;
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begin
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rs1 = {2'b01, instr_i[9:7]};
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if ((instr_i[15:13] == 3'b110) || (instr_i[15:13] == 3'b111)) begin
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imm = {instr_i[12], instr_i[6:5], instr_i[2], instr_i[11:10], instr_i[4:3]};
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regs_read.push_back('{rs1, rs1_value_i});
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end else begin
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imm = {instr_i[12], instr_i[6:2], 2'b00};
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regs_write.push_back('{rs1, 'x});
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end
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str = $sformatf("%-16s x%0d, 0x%h", mnemonic, rs1, imm);
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end
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endfunction // printCBInstr
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function void printCSInstr(input string mnemonic);
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logic [4:0] rd;
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logic [4:0] rs2;
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begin
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rd = {2'b01, instr_i[9:7]};
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rs2 = {2'b01, instr_i[4:2]};
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regs_write.push_back('{rd, 'x});
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regs_read.push_back('{rs2, rs2_value_i});
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str = $sformatf("%-16s x%0d, x%0d", mnemonic, rd, rs2);
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end
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endfunction // printCSInstr
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function void printCJInstr(input string mnemonic);
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logic [11:1] imm;
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imm = {instr_i[12], instr_i[8], instr_i[10:9], instr_i[6],
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instr_i[7], instr[2], instr[11], instr_i[5:3]};
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begin
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str = $sformatf("%-16s 0x%h", mnemonic, imm);
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end
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endfunction // printCJInstr
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function void printCompressedLoadInstr(input string mnemonic);
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logic [4:0] rd;
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logic [4:0] rs1;
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logic [7:0] imm;
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mem_acc_t mem_acc;
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begin
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// Detect C.LW intruction
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if (instr_i[1:0] == OPCODE_C0) begin
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rd = {2'b01, instr_i[4:2]};
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rs1 = {2'b01, instr_i[9:7]};
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imm = {1'b0, instr[5], instr[12:10], instr[6], 2'b00};
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end else begin
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// LWSP instruction
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rd = instr_i[11:7];
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rs1 = 5'h2;
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imm = {instr[3:2], instr[12], instr[6:4], 2'b00};
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end
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regs_write.push_back('{rd, 'x});
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regs_read.push_back('{rs1, rs1_value_i});
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str = $sformatf("%-16s x%0d, %0d(x%0d)", mnemonic, rd, rs1, imm);
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mem_acc.addr = ex_data_addr_i;
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mem_acc.rdata = ex_data_rdata_i;
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mem_access.push_back(mem_acc);
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end
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endfunction // printCompressedLoadInstr()
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function void printCompressedStoreInstr(input string mnemonic);
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logic [4:0] rs1;
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logic [4:0] rs2;
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logic [7:0] imm;
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mem_acc_t mem_acc;
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begin
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// Detect C.SW instruction
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if (instr_i[1:0] == OPCODE_C0) begin
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rs1 = {2'b01, instr_i[9:7]};
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rs2 = {2'b01, instr_i[4:2]};
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imm = {1'b0, instr[5], instr[12:10], instr[6], 2'b0};
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end else begin
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// SWSP instruction
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rs1 = 5'h2;
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rs2 = instr_i[11:7];
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imm = {instr[8:7], instr[12:9], 2'b00};
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end
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str = $sformatf("%-16s x%0d, %0d(x%0d)", mnemonic, rs2, rs1, imm);
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regs_read.push_back('{rs1, rs1_value_i});
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regs_read.push_back('{rs2, rs2_value_i});
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mem_acc.addr = ex_data_addr_i;
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mem_acc.we = 1'b1;
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mem_acc.wdata = ex_data_wdata_i;
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mem_access.push_back(mem_acc);
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end
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endfunction // printCompressedStoreInstr
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function void printLoadInstr();
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string mnemonic;
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logic [2:0] size;
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@ -317,8 +442,56 @@ module ibex_tracer #(
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trace.pc = pc_i;
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trace.instr = instr_i;
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// separate case for 'nop' instruction to avoid overlapping with 'addi'
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if (instr_i == 32'h00_00_00_13) begin
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// Check for compressed instructions
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if (instr_i[1:0] != 2'b11) begin
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// Separate case to avoid overlapping decoding
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if ((instr_i[15:13] == 3'b100) && (instr_i[1:0] == 2'b10)) begin
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if (instr_i[12]) begin
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if (instr_i[11:2] == 10'h0) begin
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trace.printMnemonic("c.ebreak");
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end else if (instr_i[6:2] == 5'b0) begin
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trace.printCRInstr("c.jalr");
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end else begin
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trace.printCRInstr("c.add");
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end
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end else begin
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if (instr_i[6:2] == 5'h0) begin
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trace.printCRInstr("c.jr");
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end else begin
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trace.printCRInstr("c.mv");
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end
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end
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end else begin
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// use casex instead of case inside due to ModelSim bug
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unique casex (instr_i)
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// C0 Opcodes
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INSTR_CADDI4SPN: trace.printCIWInstr("c.addi4spn");
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INSTR_CLW: trace.printCompressedLoadInstr("c.lw");
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INSTR_CSW: trace.printCompressedStoreInstr("c.sw");
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// C1 Opcodes
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INSTR_CADDI: trace.printCIInstr("c.addi");
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INSTR_CJAL: trace.printCJInstr("c.jal");
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INSTR_CJ: trace.printCJInstr("c.j");
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INSTR_CLI: trace.printCIInstr("c.li");
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INSTR_CLUI: trace.printCIInstr("c.lui");
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INSTR_CSRLI: trace.printCBInstr("c.srli");
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INSTR_CSRAI: trace.printCBInstr("c.srai");
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INSTR_CANDI: trace.printCBInstr("c.andi");
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INSTR_CSUB: trace.printCSInstr("c.sub");
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INSTR_CXOR: trace.printCSInstr("c.xor");
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INSTR_COR: trace.printCSInstr("c.or");
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INSTR_CAND: trace.printCSInstr("c.and");
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INSTR_CBEQZ: trace.printCBInstr("c.beqz");
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INSTR_CBNEZ: trace.printCBInstr("c.bnez");
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// C2 Opcodes
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INSTR_CSLLI: trace.printCIInstr("c.slli");
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INSTR_CLWSP: trace.printCompressedLoadInstr("c.lwsp");
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INSTR_SWSP: trace.printCompressedStoreInstr("c.swsp");
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default: trace.printMnemonic("INVALID");
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endcase // unique casex (instr_i)
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end
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end else if (instr_i == 32'h00_00_00_13) begin
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// separate case for 'nop' instruction to avoid overlapping with 'addi'
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trace.printMnemonic("nop");
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end else begin
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// use casex instead of case inside due to ModelSim bug
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@ -6,6 +6,10 @@
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package ibex_tracer_pkg;
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import ibex_pkg::*;
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parameter logic [1:0] OPCODE_C0 = 2'b00;
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parameter logic [1:0] OPCODE_C1 = 2'b01;
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parameter logic [1:0] OPCODE_C2 = 2'b10;
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// instruction masks (for tracer)
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parameter logic [31:0] INSTR_LUI = { 25'b?, {OPCODE_LUI } };
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parameter logic [31:0] INSTR_AUIPC = { 25'b?, {OPCODE_AUIPC} };
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@ -71,4 +75,36 @@ parameter logic [31:0] INSTR_STORE = {25'b?, {OPCOD
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// MISC-MEM
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parameter logic [31:0] INSTR_FENCE = { 17'b?, 3'b000, 5'b?, {OPCODE_MISC_MEM} };
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// Compressed Instructions
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// C0
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parameter logic [15:0] INSTR_CADDI4SPN = { 3'b000, 11'b?, {OPCODE_C0} };
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parameter logic [15:0] INSTR_CLW = { 3'b010, 11'b?, {OPCODE_C0} };
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parameter logic [15:0] INSTR_CSW = { 3'b110, 11'b?, {OPCODE_C0} };
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// C1
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parameter logic [15:0] INSTR_CADDI = { 3'b000, 11'b?, {OPCODE_C1} };
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parameter logic [15:0] INSTR_CJAL = { 3'b001, 11'b?, {OPCODE_C1} };
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parameter logic [15:0] INSTR_CJ = { 3'b101, 11'b?, {OPCODE_C1} };
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parameter logic [15:0] INSTR_CLI = { 3'b010, 11'b?, {OPCODE_C1} };
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parameter logic [15:0] INSTR_CLUI = { 3'b011, 11'b?, {OPCODE_C1} };
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parameter logic [15:0] INSTR_CBEQZ = { 3'b110, 11'b?, {OPCODE_C1} };
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parameter logic [15:0] INSTR_CBNEZ = { 3'b111, 11'b?, {OPCODE_C1} };
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parameter logic [15:0] INSTR_CSRLI = { 3'b100, 1'b?, 2'b00, 8'b?, {OPCODE_C1} };
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parameter logic [15:0] INSTR_CSRAI = { 3'b100, 1'b?, 2'b01, 8'b?, {OPCODE_C1} };
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parameter logic [15:0] INSTR_CANDI = { 3'b100, 1'b?, 2'b10, 8'b?, {OPCODE_C1} };
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parameter logic [15:0] INSTR_CSUB = { 3'b100, 1'b0, 2'b11, 3'b?, 2'b00, 3'b?, {OPCODE_C1} };
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parameter logic [15:0] INSTR_CXOR = { 3'b100, 1'b0, 2'b11, 3'b?, 2'b01, 3'b?, {OPCODE_C1} };
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parameter logic [15:0] INSTR_COR = { 3'b100, 1'b0, 2'b11, 3'b?, 2'b10, 3'b?, {OPCODE_C1} };
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parameter logic [15:0] INSTR_CAND = { 3'b100, 1'b0, 2'b11, 3'b?, 2'b11, 3'b?, {OPCODE_C1} };
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// C2
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parameter logic [15:0] INSTR_CSLLI = { 3'b000, 11'b?, {OPCODE_C2} };
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parameter logic [15:0] INSTR_CLWSP = { 3'b010, 11'b?, {OPCODE_C2} };
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parameter logic [15:0] INSTR_SWSP = { 3'b110, 11'b?, {OPCODE_C2} };
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parameter logic [15:0] INSTR_CMV = { 3'b100, 1'b0, 10'b?, {OPCODE_C2} };
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parameter logic [15:0] INSTR_CADD = { 3'b100, 1'b1, 10'b?, {OPCODE_C2} };
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parameter logic [15:0] INSTR_CEBREAK = { 3'b100, 1'b1, 5'b0, 5'b0, {OPCODE_C2} };
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parameter logic [15:0] INSTR_CJR = { 3'b100, 1'b0, 5'b?, 5'b0, {OPCODE_C2} };
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parameter logic [15:0] INSTR_CJALR = { 3'b100, 1'b1, 5'b?, 5'b0, {OPCODE_C2} };
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endpackage
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