[rtl] Implement mvendorid/marchid/mimpid CSRs

doc/02_user/getting_started.rst

@@ -11,3 +11,17 @@ Register File
 Ibex comes with three different register file implementations that can be selected using the enumerated parameter ``RegFile`` defined in :file:`rtl/ibex_pkg.sv`.
 Depending on the target technology, either the flip-flop-based ("ibex_pkg::RegFileFF", default), the latch-based ("ibex_pkg::RegFileLatch") or an FPGA-targeted ("ibex_pkg::RegFileFPGA") implementation should be selected.
 For more information about the three register file implementations and their trade-offs, check out :ref:`register-file`.
+
+Identification CSRs
+-------------------
+
+The RISC-V Privileged Architecture specifies several read-only CSRs that identify the vendor and micro-architecture of a CPU.
+These are ``mvendorid``, ``marchid`` and ``mimpid``.
+The fixed, read-only values for these CSRs are defined in :file:`rtl/ibex_pkg.sv`.
+Implementers should carefully consider appropriate values for these registers.
+Ibex, as an open source implementation, has an assigned architecture ID (``marchid``) of 22.
+(Allocations are specified in `marchid.md of the riscv-isa-manual repository <https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md>`_.)
+If significant changes are made to the micro-architecture a different architecture ID should be used.
+The vendor ID and implementation ID (``mvendorid`` and ``mimpid``) both read as 0 by default, meaning non-implemented.
+Implementers may wish to use other values here.
+Please see the RISC-V Privileged Architecture specification for more details on what these IDs represent and how they should be chosen.

doc/03_reference/cs_registers.rst

@@ -94,6 +94,12 @@ Ibex implements all the Control and Status Registers (CSRs) listed in the follow
 +---------+--------------------+--------+-----------------------------------------------+
 |  0xB9F  | ``mhpmcounter31h`` | WARL   | Upper 32 bits of ``mhmpcounter31``            |
 +---------+--------------------+--------+-----------------------------------------------+
+|  0xF11  | ``mvendorid``      | R      | Machine Vendor ID                             |
++---------+--------------------+--------+-----------------------------------------------+
+|  0xF12  | ``marchid``        | R      | Machine Architecture ID                       |
++---------+--------------------+--------+-----------------------------------------------+
+|  0xF13  | ``mimpid``         | R      | Machine Implementation ID                     |
++---------+--------------------+--------+-----------------------------------------------+
 |  0xF14  | ``mhartid``        | R      | Hardware Thread ID                            |
 +---------+--------------------+--------+-----------------------------------------------+
 
@@ -576,6 +582,38 @@ The User Mode ``time(h)`` registers are not implemented in Ibex.
 Any access to these registers will trap.
 It is recommended that trap handler software provides a means of accessing platform-defined ``mtime(h)`` timers where available.
 
+Machine Vendor ID (mvendorid)
+-----------------------------
+
+CSR Address: ``0xF11``
+
+Reset Value: ``0x0000_0000``
+
+Use the ``CSR_MVENDORID_VALUE`` parameter in :file:`rtl/ibex_pkg.sv` to change the fixed value.
+Details of what the ID represents can be found in the RISC-V Privileged Specification.
+
+Machine Architecture ID (marchid)
+---------------------------------
+
+CSR Address: ``0xF12``
+
+Reset Value: ``0x0000_0016``
+
+Use the ``CSR_MARCHID_VALUE`` parameter in :file:`rtl/ibex_pkg.sv` to change the fixed value.
+The value used is allocated specifically to Ibex.
+If significant changes are made a different ID should be used.
+Details of what the ID represents can be found in the RISC-V Privileged Specification.
+
+Machine Implementation ID (mimpid)
+----------------------------------
+
+CSR Address: ``0xF13``
+
+Reset Value: ``0x0000_0000``
+
+Use the ``CSR_MIMPID_VALUE`` parameter in :file:`rtl/ibex_pkg.sv` to change the fixed value.
+Details of what the ID represents can be found in the RISC-V Privileged Specification.
+
 .. _csr-mhartid:
 
 Hardware Thread ID (mhartid)

dv/uvm/core_ibex/riscv_dv_extension/csr_description.yaml

@@ -63,6 +63,58 @@
 #      msb: 25
 #      lsb: 0
 
+# CSR test generation cannot deal with read-only fields. Leaving these here
+# commented out so they can be used once the read-only issue is fixed.
+# https://github.com/lowRISC/ibex/issues/1337 tracks the required improvements
+#- csr: mvendorid
+#  description: >
+#    Machine Vendor ID Register providing JEDEC manufacturer ID
+#  address: 0xF11
+#  privilege_mode: M
+#  rv32:
+#    - field_name: Bank
+#      description: >
+#        Number of continuation codes in JEDEC ID
+#      type: R
+#      reset_val: 0
+#      msb: 31
+#      lsb: 7
+#    - field_name: Offset
+#      description: >
+#        JEDEC ID final byte
+#      type: R
+#      reset_val: 0
+#      msb: 6
+#      lsb: 0
+#
+#- csr: marchid
+#  description: >
+#    Machine Architecture ID Register
+#  address: 0xF12
+#  privilege_mode: M
+#  rv32:
+#    - field_name: Architecture ID
+#      description: >
+#        ID indicating the base microarchitecture
+#      type: R
+#      reset_val: 22
+#      msb: 31
+#      lsb: 0
+#
+#- csr: mimpid
+#  description: >
+#    Machine Implementation ID Register
+#  address: 0xF13
+#  privilege_mode: M
+#  rv32:
+#    - field_name: Implementation
+#      description: >
+#        Unique encoding of processor implementation version
+#      type: R
+#      reset_val: 0
+#      msb: 31
+#      lsb: 0
+
 # Ibex's implementation of MHARTID is read-only
 # MHARTID
 #- csr: mhartid

rtl/ibex_cs_registers.sv

@@ -294,6 +294,12 @@ module ibex_cs_registers #(
     illegal_csr   = 1'b0;
 
     unique case (csr_addr_i)
+      // mvendorid: encoding of manufacturer/provider
+      CSR_MVENDORID: csr_rdata_int = CSR_MVENDORID_VALUE;
+      // marchid: encoding of base microarchitecture
+      CSR_MARCHID: csr_rdata_int = CSR_MARCHID_VALUE;
+      // mimpid: encoding of processor implementation version
+      CSR_MIMPID: csr_rdata_int = CSR_MIMPID_VALUE;
       // mhartid: unique hardware thread id
       CSR_MHARTID: csr_rdata_int = hart_id_i;
 

rtl/ibex_pkg.sv

@@ -377,6 +377,9 @@ package ibex_pkg;
   // CSRs
   typedef enum logic[11:0] {
     // Machine information
+    CSR_MVENDORID = 12'hF11,
+    CSR_MARCHID   = 12'hF12,
+    CSR_MIMPID    = 12'hF13,
     CSR_MHARTID   = 12'hF14,
 
     // Machine trap setup
@@ -559,6 +562,23 @@ package ibex_pkg;
   parameter int unsigned CSR_MSECCFG_MMWP_BIT = 1;
   parameter int unsigned CSR_MSECCFG_RLB_BIT  = 2;
 
+  // Vendor ID
+  // No JEDEC ID has been allocated to lowRISC so the value is 0 to indicate the field is not
+  // implemented
+  localparam logic [31:0] CSR_MVENDORID_VALUE  = 32'b0;
+
+  // Architecture ID
+  // Top bit is unset to indicate an open source project. The lower bits are an ID allocated by the
+  // RISC-V Foundation. Note this is allocated specifically to Ibex, should significant changes be
+  // made a different architecture ID should be supplied.
+  localparam logic [31:0] CSR_MARCHID_VALUE = {1'b0, 31'd22};
+
+  // Implementation ID
+  // 0 indicates this field is not implemeted. Ibex implementors may wish to indicate an RTL/netlist
+  // version here using their own unique encoding (e.g. 32 bits of the git hash of the implemented
+  // commit).
+  localparam logic [31:0] CSR_MIMPID_VALUE = 32'b0;
+
   // These LFSR parameters have been generated with
   // $ opentitan/util/design/gen-lfsr-seed.py --width 32 --seed 2480124384 --prefix ""
   parameter int LfsrWidth = 32;