Update paths for vendored DV code

This commit amends some paths in the vendoring hjson file (and updates
config files to use things at the new paths). Finally it re-runs the
vendoring tool:

  Update code from upstream repository
  https://github.com/lowRISC/opentitan to revision
  92e9242424c72c59008e267dd3779e2af5ec8e83

which just ends up with a load of file renames.

Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>

doc/03_reference/verification.rst

@@ -51,7 +51,7 @@ Memory Model
 """"""""""""
 
 The code is vendored from OpenTitan and can be found in the
-`vendor/lowrisc_ip/mem_model <https://github.com/lowRISC/ibex/tree/master/vendor/lowrisc_ip/mem_model>`_
+`vendor/lowrisc_ip/dv/sv/mem_model <https://github.com/lowRISC/ibex/tree/master/vendor/lowrisc_ip/dv/sv/mem_model>`_
 directory.
 The testbench instantiates a single instance of this memory model that it loads the compiled
 assembly test program into at the beginning of each test.
@@ -253,7 +253,7 @@ the Ibex repository:
 
 .. code-block:: bash
 
-   ./vendor/lowrisc_ip/dvsim/dvsim.py dv/uvm/icache/dv/ibex_icache_sim_cfg.hjson --build-only
+   ./vendor/lowrisc_ip/util/dvsim/dvsim.py dv/uvm/icache/dv/ibex_icache_sim_cfg.hjson --build-only
    --skip-ral --purge --sr sim_out
 
 Specify the intended output directory using either the ``--sr`` or ``-scratch-root`` option.

dv/uvm/core_ibex/ibex_dv.f

@@ -9,23 +9,23 @@
 +define+RVFI
 
 // Shared lowRISC code
-+incdir+${PRJ_DIR}/vendor/lowrisc_ip/prim/rtl
-${PRJ_DIR}/vendor/lowrisc_ip/prim/rtl/prim_assert.sv
-${PRJ_DIR}/vendor/lowrisc_ip/prim/rtl/prim_lfsr.sv
-${PRJ_DIR}/vendor/lowrisc_ip/prim/rtl/prim_secded_28_22_enc.sv
-${PRJ_DIR}/vendor/lowrisc_ip/prim/rtl/prim_secded_28_22_dec.sv
-${PRJ_DIR}/vendor/lowrisc_ip/prim/rtl/prim_secded_39_32_enc.sv
-${PRJ_DIR}/vendor/lowrisc_ip/prim/rtl/prim_secded_39_32_dec.sv
-${PRJ_DIR}/vendor/lowrisc_ip/prim/rtl/prim_secded_72_64_enc.sv
-${PRJ_DIR}/vendor/lowrisc_ip/prim/rtl/prim_secded_72_64_dec.sv
++incdir+${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl
+${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_assert.sv
+${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_lfsr.sv
+${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_28_22_enc.sv
+${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_28_22_dec.sv
+${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_39_32_enc.sv
+${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_39_32_dec.sv
+${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_72_64_enc.sv
+${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_72_64_dec.sv
 
 // Until this list is generated by FuseSoC, we have to use manually generated
 // wrappers around the prim_* modules to instantiate the prim_generic_* ones,
 // see https://github.com/lowRISC/ibex/issues/893.
 ${PRJ_DIR}/dv/uvm/core_ibex/common/prim/prim_pkg.sv
-${PRJ_DIR}/vendor/lowrisc_ip/prim_generic/rtl/prim_generic_ram_1p.sv
+${PRJ_DIR}/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_ram_1p.sv
 ${PRJ_DIR}/dv/uvm/core_ibex/common/prim/prim_ram_1p.sv
-${PRJ_DIR}/vendor/lowrisc_ip/prim_generic/rtl/prim_generic_clock_gating.sv
+${PRJ_DIR}/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_gating.sv
 ${PRJ_DIR}/dv/uvm/core_ibex/common/prim/prim_clock_gating.sv
 
 // ibex CORE RTL files
@@ -65,13 +65,13 @@ ${PRJ_DIR}/vendor/google_riscv-dv/src/riscv_signature_pkg.sv
 +incdir+${PRJ_DIR}/dv/uvm/core_ibex/tests
 +incdir+${PRJ_DIR}/dv/uvm/core_ibex/common/ibex_mem_intf_agent
 +incdir+${PRJ_DIR}/dv/uvm/core_ibex/common/irq_agent
-+incdir+${PRJ_DIR}/vendor/lowrisc_ip/mem_model
-+incdir+${PRJ_DIR}/vendor/lowrisc_ip/dv_utils
++incdir+${PRJ_DIR}/vendor/lowrisc_ip/dv/sv/mem_model
++incdir+${PRJ_DIR}/vendor/lowrisc_ip/dv/sv/dv_utils
 ${PRJ_DIR}/dv/uvm/bus_params_pkg/bus_params_pkg.sv
-${PRJ_DIR}/vendor/lowrisc_ip/common_ifs/clk_rst_if.sv
-${PRJ_DIR}/vendor/lowrisc_ip/common_ifs/pins_if.sv
-${PRJ_DIR}/vendor/lowrisc_ip/dv_utils/dv_utils_pkg.sv
-${PRJ_DIR}/vendor/lowrisc_ip/mem_model/mem_model_pkg.sv
+${PRJ_DIR}/vendor/lowrisc_ip/dv/sv/common_ifs/clk_rst_if.sv
+${PRJ_DIR}/vendor/lowrisc_ip/dv/sv/common_ifs/pins_if.sv
+${PRJ_DIR}/vendor/lowrisc_ip/dv/sv/dv_utils/dv_utils_pkg.sv
+${PRJ_DIR}/vendor/lowrisc_ip/dv/sv/mem_model/mem_model_pkg.sv
 ${PRJ_DIR}/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf.sv
 ${PRJ_DIR}/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_agent_pkg.sv
 ${PRJ_DIR}/dv/uvm/core_ibex/common/irq_agent/irq_if.sv

dv/uvm/icache/doc/ibex_icache_dv_plan.md

@@ -20,7 +20,7 @@ The ICache design is documented in the [Instruction Cache](https://ibex-core.rea
 
 ## Testbench architecture
 
-The testbench is built using the [DV_LIB testbench architecture](https://github.com/lowRISC/ibex/tree/master/vendor/lowrisc_ip/dv_lib/).
+The testbench is built using the [DV_LIB testbench architecture](https://github.com/lowRISC/ibex/tree/master/vendor/lowrisc_ip/dv/sv/dv_lib/).
 
 The testbench intentionally avoids knowing detailed information about the cache's performance characteristics (for example, cache size, line size or number of ways).
 This means that the testbench cannot compare the DUT with a reference model, nor can it model the exact requests that the DUT will make of instruction memory: the whole point of a cache is that it might avoid an instruction fetch.
@@ -86,7 +86,7 @@ The sole sequence causes occasional 1- or 2-bit errors, injected by XORing valid
 
 The top level testbench is located at [`dv/uvm/icache/dv/tb/tb.sv`](https://github.com/lowRISC/ibex/blob/master/dv/uvm/icache/dv/tb/tb.sv). It instantiates the `ibex_icache` DUT module whose source is at [`rtl/ibex_icache.sv`](https://github.com/lowRISC/ibex/blob/master/rtl/ibex_icache.sv).
 In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into `uvm_config_db`:
-* Clock and reset interface ([`vendor/lowrisc_ip/common_ifs`](https://github.com/lowRISC/ibex/tree/master/vendor/lowrisc_ip/common_ifs))
+* Clock and reset interface ([`vendor/lowrisc_ip/dv/sv/common_ifs`](https://github.com/lowRISC/ibex/tree/master/vendor/lowrisc_ip/dv/sv/common_ifs))
 * Core interface ([`dv/uvm/icache/dv/ibex_icache_core_agent/ibex_icache_core_if.sv`](https://github.com/lowRISC/ibex/blob/master/dv/uvm/icache/dv/ibex_icache_core_agent/ibex_icache_core_if.sv))
 * Memory interface ([`dv/uvm/icache/dv/ibex_icache_mem_agent/ibex_icache_mem_if.sv`](https://github.com/lowRISC/ibex/blob/master/dv/uvm/icache/dv/ibex_icache_mem_agent/ibex_icache_mem_if.sv))
 * ECC interfaces ([`dv/uvm/icache/dv/ibex_icache_ecc_agent/ibex_icache_ecc_if.sv`](https://github.com/lowRISC/ibex/blob/master/dv/uvm/icache/dv/ibex_icache_ecc_agent/ibex_icache_ecc_if.sv))
@@ -142,7 +142,7 @@ To do so, we would just need to monitor fetches in the memory agent as well as s
 
 ## Building and running tests
 
-Tests are built and run with the [`dvsim`](https://github.com/lowRISC/ibex/tree/master/vendor/lowrisc_ip/dvsim) tool (vendored in from the OpenTitan project).
+Tests are built and run with the [`dvsim`](https://github.com/lowRISC/ibex/tree/master/vendor/lowrisc_ip/util/dvsim) tool (vendored in from the OpenTitan project).
 To ensure output files end up in the right place without ugly command lines, this is wrapped up in a Makefile.
 To run the test suite, run:
 

dv/uvm/icache/dv/Makefile

@@ -30,7 +30,7 @@ TESTS=
 
 ibex-top       := ../../../..
 scratch-root   := $(ibex-top)/build
-dvsim-py       := $(ibex-top)/vendor/lowrisc_ip/dvsim/dvsim.py
+dvsim-py       := $(ibex-top)/vendor/lowrisc_ip/util/dvsim/dvsim.py
 dvsim-std-args := --scratch-root $(scratch-root)
 
 waves-arg      := $(if $(filter-out 0,$(WAVES)),--waves,)

vendor/lowrisc_ip.vendor.hjson

@@ -11,34 +11,34 @@
     }
 
     mapping: [
-        {from: "hw/dv/sv/common_ifs",  to: "common_ifs"},
-        {from: "hw/dv/sv/csr_utils",   to: "csr_utils"},
-        {from: "hw/dv/sv/dv_base_reg", to: "dv_base_reg"},
-        {from: "hw/dv/sv/mem_model",   to: "mem_model"},
-        {from: "hw/dv/verilator",      to: "dv_verilator"},
+        {from: "hw/dv/sv/common_ifs",  to: "dv/sv/common_ifs"},
+        {from: "hw/dv/sv/csr_utils",   to: "dv/sv/csr_utils"},
+        {from: "hw/dv/sv/dv_base_reg", to: "dv/sv/dv_base_reg"},
+        {from: "hw/dv/sv/mem_model",   to: "dv/sv/mem_model"},
+        {from: "hw/dv/verilator",      to: "dv/verilator"},
 
         // We apply a patch to fix the bus_params_pkg core file name when
         // vendoring in dv_lib and dv_utils. This allows us to have an
         // Ibex-specific core file for these defines.
         {
             from:      "hw/dv/sv/dv_lib",
-            to:        "dv_lib",
+            to:        "dv/sv/dv_lib",
             patch_dir: "dv_lib",
         },
         {
             from:      "hw/dv/sv/dv_utils",
-            to:        "dv_utils",
+            to:        "dv/sv/dv_utils",
             patch_dir: "dv_utils",
         },
 
-        {from: "hw/ip/prim",           to: "prim"},
-        {from: "hw/ip/prim_generic",   to: "prim_generic"},
-        {from: "hw/ip/prim_xilinx",    to: "prim_xilinx"},
+        {from: "hw/ip/prim",           to: "ip/prim"},
+        {from: "hw/ip/prim_generic",   to: "ip/prim_generic"},
+        {from: "hw/ip/prim_xilinx",    to: "ip/prim_xilinx"},
 
         {from: "hw/lint",              to: "lint"},
 
-        {from: "util/dvsim",           to: "dvsim"},
-        {from: "util/uvmdvgen",        to: "uvmdvgen"},
+        {from: "util/dvsim",           to: "util/dvsim"},
+        {from: "util/uvmdvgen",        to: "util/uvmdvgen"},
     ]
 
     patch_dir: "patches/lowrisc_ip"