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Add hwloop decoding
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Sven Stucki
parent
5a38967a0c
commit
6aa40c336d
4 changed files with 56 additions and 71 deletions
105
controller.sv
105
controller.sv
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@ -869,80 +869,71 @@ module controller
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end
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/*
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///////////////////////////////////////////////
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// _ ___ ___ ___ ___ ____ //
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// | | | \ \ / / | / _ \ / _ \| _ \ //
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// | |_| |\ \ /\ / /| | | | | | | | | |_) | //
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// | _ | \ V V / | |__| |_| | |_| | __/ //
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// |_| |_| \_/\_/ |_____\___/ \___/|_| //
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// //
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///////////////////////////////////////////////
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`OPCODE_HWLOOP: begin // hwloop instructions
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hwloop_regid_o = instr_rdata_i[22:21]; // set hwloop register id
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case (instr_rdata_i[25:23])
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3'b000,3'b110,3'b111: begin // lp.start set start address
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hwloop_wb_mux_sel_o = 1'b1;
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hwloop_we_o[0] = 1'b1; // set we for start addr reg
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alu_op_a_mux_sel_o = `OP_A_CURRPC;
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alu_op_b_mux_sel_o = `OP_B_IMM;
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alu_operator = `ALU_ADD;
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alu_pc_mux_sel_o = 1'b1;
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immediate_mux_sel_o = `IMM_21S;
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// $display("%t: hwloop start address: %h", $time, instr_rdata_i);
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`OPCODE_HWLOOP: begin // hardware loop instructions
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unique case (instr_rdata_i[14:12])
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3'b000: begin // lp.starti set start address
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hwloop_wb_mux_sel_o = 1'b1;
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hwloop_we_o[0] = 1'b1; // set we for start addr reg
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alu_op_a_mux_sel_o = `OP_A_CURRPC;
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alu_op_b_mux_sel_o = `OP_B_IMM;
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alu_operator = `ALU_ADD;
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// $display("%t: hwloop start address: %h", $time, instr_rdata_i);
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end
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3'b001: begin // lp.end set end address
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hwloop_wb_mux_sel_o = 1'b1;
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hwloop_we_o[1] = 1'b1; // set we for end addr reg
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alu_op_a_mux_sel_o = `OP_A_CURRPC;
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alu_op_b_mux_sel_o = `OP_B_IMM;
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alu_operator = `ALU_ADD;
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alu_pc_mux_sel_o = 1'b1;
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immediate_mux_sel_o = `IMM_21S;
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// $display("%t: hwloop end address: %h", $time, instr_rdata_i);
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3'b001: begin // lp.endi set end address
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hwloop_wb_mux_sel_o = 1'b1;
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hwloop_we_o[1] = 1'b1; // set we for end addr reg
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alu_op_a_mux_sel_o = `OP_A_CURRPC;
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alu_op_b_mux_sel_o = `OP_B_IMM;
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alu_operator = `ALU_ADD;
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// $display("%t: hwloop end address: %h", $time, instr_rdata_i);
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end
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3'b010: begin // lp.counti initialize counter from immediate
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hwloop_cnt_mux_sel_o = 2'b01;
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hwloop_we_o[2] = 1'b1; // set we for counter reg
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// $display("%t: hwloop counter imm: %h", $time, instr_rdata_i);
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3'b010: begin // lp.count initialize counter from register
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hwloop_cnt_mux_sel_o = 2'b11;
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hwloop_we_o[2] = 1'b1; // set we for counter reg
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rega_used = 1'b1;
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// $display("%t: hwloop counter: %h", $time, instr_rdata_i);
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end
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3'b011: begin // lp.count initialize counter from register
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hwloop_cnt_mux_sel_o = 2'b11;
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hwloop_we_o[2] = 1'b1; // set we for counter reg
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rega_used = 1'b1;
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// $display("%t: hwloop counter: %h", $time, instr_rdata_i);
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3'b011: begin // lp.counti initialize counter from immediate
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hwloop_cnt_mux_sel_o = 2'b01;
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hwloop_we_o[2] = 1'b1; // set we for counter reg
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// $display("%t: hwloop counter imm: %h", $time, instr_rdata_i);
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end
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3'b100: begin // lp.setupi
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hwloop_wb_mux_sel_o = 1'b0;
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hwloop_cnt_mux_sel_o = 2'b10;
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hwloop_we_o = 3'b111; // set we for counter/start/end reg
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alu_op_a_mux_sel_o = `OP_A_CURRPC;
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alu_op_b_mux_sel_o = `OP_B_IMM;
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alu_operator = `ALU_ADD;
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alu_pc_mux_sel_o = 1'b1;
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immediate_mux_sel_o = `IMM_8Z;
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// $display("%t: hwloop setup imm: %h", $time, instr_rdata_i);
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3'b100: begin // lp.setup
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hwloop_wb_mux_sel_o = 1'b0;
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hwloop_cnt_mux_sel_o = 2'b11;
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hwloop_we_o = 3'b111; // set we for counter/start/end reg
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alu_op_a_mux_sel_o = `OP_A_CURRPC;
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alu_op_b_mux_sel_o = `OP_B_IMM;
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alu_operator = `ALU_ADD;
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// TODO: immediate_mux_sel_o = `IMM_16Z;
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rega_used = 1'b1;
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// $display("%t: hwloop setup: %h", $time, instr_rdata_i);
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end
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3'b101: begin // lp.setup
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hwloop_wb_mux_sel_o = 1'b0;
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hwloop_cnt_mux_sel_o = 2'b11;
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hwloop_we_o = 3'b111; // set we for counter/start/end reg
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alu_op_a_mux_sel_o = `OP_A_CURRPC;
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alu_op_b_mux_sel_o = `OP_B_IMM;
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alu_operator = `ALU_ADD;
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alu_pc_mux_sel_o = 1'b1;
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immediate_mux_sel_o = `IMM_16Z;
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rega_used = 1'b1;
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// $display("%t: hwloop setup: %h", $time, instr_rdata_i);
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3'b101: begin // lp.setupi
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hwloop_wb_mux_sel_o = 1'b0;
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hwloop_cnt_mux_sel_o = 2'b10;
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hwloop_we_o = 3'b111; // set we for counter/start/end reg
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alu_op_a_mux_sel_o = `OP_A_CURRPC;
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alu_op_b_mux_sel_o = `OP_B_IMM;
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alu_operator = `ALU_ADD;
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// TODO: immediate_mux_sel_o = `IMM_8Z;
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// $display("%t: hwloop setup imm: %h", $time, instr_rdata_i);
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end
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default: begin
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illegal_insn_int = 1'b1;
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end
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endcase
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end
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*/
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default: begin
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illegal_insn_int = 1'b1;
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end
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@ -712,7 +712,6 @@ module id_stage
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// //
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//////////////////////////////////////////////////////////////////////////
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/*
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hwloop_controller hwloop_controller_i
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(
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// from ID stage
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@ -733,8 +732,6 @@ module id_stage
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// to hwloop_regs
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.hwloop_dec_cnt_o ( hwloop_dec_cnt_o )
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);
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*/
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/////////////////////////////////////////////////////////////////////////////////
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@ -56,6 +56,7 @@
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// PULP custom
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`define OPCODE_STORE_POST 7'h27
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`define OPCODE_LOAD_POST 7'h07
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`define OPCODE_HWLOOP 7'h6b
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// instruction masks (for tracer)
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@ -179,6 +179,7 @@ module riscv_core
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logic save_pc_if;
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logic save_pc_id;
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// hwloop data from ALU
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logic [31:0] hwlp_cnt_ex; // from id to ex stage (hwloop_regs)
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logic [2:0] hwlp_we_ex; // from id to ex stage (hwloop_regs)
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@ -188,7 +189,6 @@ module riscv_core
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logic [31:0] hwlp_end_data_ex; // hwloop data to write to hwloop_regs
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logic [31:0] hwlp_cnt_data_ex; // hwloop data to write to hwloop_regs
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// Access to hwloop registers
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logic [31:0] hwlp_start_data;
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logic [31:0] hwlp_end_data;
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@ -606,7 +606,7 @@ module riscv_core
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.ext_counters_i ( ext_perf_counters_i )
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);
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// Mux for SPR access through Debug Unit
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// Mux for CSR access through Debug Unit
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assign csr_addr = (dbg_sp_mux == 1'b0) ? alu_operand_b_ex[11:0] : dbg_reg_addr;
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assign csr_wdata = (dbg_sp_mux == 1'b0) ? alu_operand_a_ex : dbg_reg_wdata;
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assign csr_op = (dbg_sp_mux == 1'b0) ? csr_op_ex
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@ -614,8 +614,6 @@ module riscv_core
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assign dbg_rdata = (dbg_sp_mux == 1'b0) ? dbg_reg_rdata : csr_rdata;
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/*
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//////////////////////////////////////////////
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// Hardware Loop Registers //
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//////////////////////////////////////////////
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@ -643,13 +641,11 @@ module riscv_core
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.hwloop_dec_cnt_i ( hwlp_dec_cnt )
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);
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// write to hwloop registers via SPR or instructions
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assign hwlp_start_data = (hwlp_we_ex[0] == 1'b1) ? hwlp_start_data_ex : sp_hwlp_start;
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assign hwlp_end_data = (hwlp_we_ex[1] == 1'b1) ? hwlp_end_data_ex : sp_hwlp_end;
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assign hwlp_cnt_data = (hwlp_we_ex[2] == 1'b1) ? hwlp_cnt_data_ex : sp_hwlp_cnt;
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assign hwlp_regid = (|hwlp_we_ex) ? hwlp_regid_ex : sp_hwlp_regid;
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assign hwlp_we = hwlp_we_ex | sp_hwlp_we;
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*/
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assign hwlp_start_data = hwlp_start_data_ex;
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assign hwlp_end_data = hwlp_end_data_ex;
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assign hwlp_cnt_data = hwlp_cnt_data_ex;
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assign hwlp_regid = hwlp_regid_ex;
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assign hwlp_we = hwlp_we_ex;
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/////////////////////////////////////////////////////////////
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