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[Doc] Added extra setup info for Verification

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Greg Chadwick 2019-10-16 16:55:46 +01:00
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doc/verification.rst
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@ -30,11 +30,13 @@ Please note that this work is still working in progress.
Getting Started
---------------
Prerequisites
~~~~~~~~~~~~~
Prerequisites & Environment Setup
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- VCS RTL simulator (need to support UVM 1.2)
- `Setup the RISC-V instruction generator and ISS sim environment <https://github.com/google/riscv-dv#getting-started>`_
- VCS RTL simulator (needed to support UVM 1.2)
- RISCV-DV Prerequisites - https://github.com/google/riscv-dv#prerequisites
- GCC setup - https://github.com/google/riscv-dv#compile-generated-programs-with-gcc
- ISS setup - https://github.com/google/riscv-dv#run-iss-instruction-set-simulator-simulation - note that commit log must be enabled in spike by passing ``--enable-commitlog`` to the configure script.
End-to-end RTL/ISS co-simulation flow
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~