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Implement Verilator-compatible tracer, and use it
The ibex_tracer module implements an execution tracer, observing the execution flow and writing a human-readable execution trace. The trace information is coming from the RVFI signals, as specified at https://github.com/SymbioticEDA/riscv-formal/blob/master/docs/rvfi.md. The existing implementation was tailored for use in ModelSim and other commercial simulators, and used SystemVerilog features which are not supported in Verilator or Icarus Verilog, such as classes, queues and non-standard format specifiers (e.g. the `-` specifier for right-aligned output). Being unable to see an execution trace when using Verilator significantly reduced productivity and its usefulness. This commit refactors the tracer to only use SystemVerilog constructs which are supported in Verilator. While doing so, multiple improvements were made for correctness and style. Major changes: - Improve compatibility with Verilator. Remove many non-synthesizable SystemVerilog constructs, such as classes and queues. Use casez instead of casex for better Verilator support (Verilator doesn't support X). - Make the decoded output of the tracer match objdump from binutils exactly. Doing so is beneficial for two reasons: we can easily cross-check the decoded output from the tracer against the disassembly produced by objdump (and we did that), and users don't need to get used to another slighly different disassembly format. - A plusarg "+ibex_tracer_file_base=ibex_my_trace" can be used to set a different basename for the trace log file. Smaller cleanups: - Remove decoding of reg-reg loads, which were leftover from a PULP extension. - Make better use of the data available on the RVFI. Pass all of RVFI to the tracer, and use the provided data instead of manually recreating it, e.g. to get register data or the jump target. - Rename all "instr" abbreviations to "insn". "insn" is what RVFI uses (and we cannot change that), so for consistency we now always use this abbreviation across the file. All CSR names have been imported from binutils' riscv-opc.h file, available at https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=include/opcode/riscv-opc.h using this small C program: #include <stdio.h> #define STR(s) #s int main(int argc, char **argv) { printf("unique case (csr_addr)\n"); #define DECLARE_CSR(name, csraddr) \ printf(" 12'd%d: return \"%s\";\n", csraddr, STR(name)); #include "riscv-opc.h" printf(" default: return $sformatf(\"0x%%x\", csr_addr);\n"); printf("endcase\n"); return 0; } The RISC-V compliance test suite for the RV32 I, M, and C extensions has been executed and traced. The disassembly of all traces have been compared against traces produced by objdump to ensure identical output. This PR is based on work by Rahul Behl <raulbehl@gmail.com> in #280. Thank you Rahul for providing a great starting point for this work!
This commit is contained in:
Philipp Wagner
Philipp Wagner
parent
e420688d1c
commit
74780e7e17
4 changed files with 883 additions and 627 deletions
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@ -5,7 +5,3 @@ Tracer
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The module ``ibex_tracer`` can be used to create a log of the executed instructions.
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It is used by ``ibex_core_tracing`` which forwards the signals added by :ref:`rvfi` as an input for the tracer.
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.. note::
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``ibex_tracer`` is not compatible with Verilator.
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@ -158,28 +158,33 @@ module ibex_core_tracing #(
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.core_sleep_o
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);
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ibex_tracer
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u_ibex_tracer (
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.clk_i,
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.rst_ni,
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`ifndef VERILATOR
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ibex_tracer u_ibex_tracer (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.hart_id_i,
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.fetch_enable_i ( fetch_enable_i ),
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.hart_id_i ( hart_id_i ),
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.valid_i ( rvfi_valid ),
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.pc_i ( rvfi_pc_rdata ),
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.instr_i ( rvfi_insn ),
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.rs1_value_i ( rvfi_rs1_rdata ),
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.rs2_value_i ( rvfi_rs2_rdata ),
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.ex_reg_addr_i ( rvfi_rd_addr ),
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.ex_reg_wdata_i ( rvfi_rd_wdata ),
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.ex_data_addr_i ( rvfi_mem_addr ),
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.ex_data_wdata_i ( rvfi_mem_wdata ),
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.ex_data_rdata_i ( rvfi_mem_rdata )
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.rvfi_valid,
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.rvfi_order,
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.rvfi_insn,
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.rvfi_trap,
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.rvfi_halt,
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.rvfi_intr,
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.rvfi_mode,
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.rvfi_rs1_addr,
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.rvfi_rs2_addr,
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.rvfi_rs1_rdata,
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.rvfi_rs2_rdata,
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.rvfi_rd_addr,
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.rvfi_rd_wdata,
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.rvfi_pc_rdata,
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.rvfi_pc_wdata,
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.rvfi_mem_addr,
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.rvfi_mem_rmask,
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.rvfi_mem_wmask,
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.rvfi_mem_rdata,
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.rvfi_mem_wdata
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);
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`else
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// ibex_tracer uses language constructs which Verilator doesn't understand.
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`endif
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endmodule
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1303
rtl/ibex_tracer.sv
1303
rtl/ibex_tracer.sv
File diff suppressed because it is too large
Load diff
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@ -11,100 +11,104 @@ parameter logic [1:0] OPCODE_C1 = 2'b01;
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parameter logic [1:0] OPCODE_C2 = 2'b10;
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// instruction masks (for tracer)
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parameter logic [31:0] INSTR_LUI = { 25'b?, {OPCODE_LUI } };
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parameter logic [31:0] INSTR_AUIPC = { 25'b?, {OPCODE_AUIPC} };
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parameter logic [31:0] INSTR_JAL = { 25'b?, {OPCODE_JAL } };
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parameter logic [31:0] INSTR_JALR = { 17'b?, 3'b000, 5'b?, {OPCODE_JALR } };
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parameter logic [31:0] INSN_LUI = { 25'b?, {OPCODE_LUI } };
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parameter logic [31:0] INSN_AUIPC = { 25'b?, {OPCODE_AUIPC} };
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parameter logic [31:0] INSN_JAL = { 25'b?, {OPCODE_JAL } };
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parameter logic [31:0] INSN_JALR = { 17'b?, 3'b000, 5'b?, {OPCODE_JALR } };
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// BRANCH
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parameter logic [31:0] INSTR_BEQ = { 17'b?, 3'b000, 5'b?, {OPCODE_BRANCH} };
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parameter logic [31:0] INSTR_BNE = { 17'b?, 3'b001, 5'b?, {OPCODE_BRANCH} };
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parameter logic [31:0] INSTR_BLT = { 17'b?, 3'b100, 5'b?, {OPCODE_BRANCH} };
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parameter logic [31:0] INSTR_BGE = { 17'b?, 3'b101, 5'b?, {OPCODE_BRANCH} };
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parameter logic [31:0] INSTR_BLTU = { 17'b?, 3'b110, 5'b?, {OPCODE_BRANCH} };
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parameter logic [31:0] INSTR_BGEU = { 17'b?, 3'b111, 5'b?, {OPCODE_BRANCH} };
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parameter logic [31:0] INSTR_BALL = { 17'b?, 3'b010, 5'b?, {OPCODE_BRANCH} };
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parameter logic [31:0] INSN_BEQ = { 17'b?, 3'b000, 5'b?, {OPCODE_BRANCH} };
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parameter logic [31:0] INSN_BNE = { 17'b?, 3'b001, 5'b?, {OPCODE_BRANCH} };
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parameter logic [31:0] INSN_BLT = { 17'b?, 3'b100, 5'b?, {OPCODE_BRANCH} };
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parameter logic [31:0] INSN_BGE = { 17'b?, 3'b101, 5'b?, {OPCODE_BRANCH} };
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parameter logic [31:0] INSN_BLTU = { 17'b?, 3'b110, 5'b?, {OPCODE_BRANCH} };
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parameter logic [31:0] INSN_BGEU = { 17'b?, 3'b111, 5'b?, {OPCODE_BRANCH} };
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parameter logic [31:0] INSN_BALL = { 17'b?, 3'b010, 5'b?, {OPCODE_BRANCH} };
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// OPIMM
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parameter logic [31:0] INSTR_ADDI = { 17'b?, 3'b000, 5'b?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSTR_SLTI = { 17'b?, 3'b010, 5'b?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSTR_SLTIU = { 17'b?, 3'b011, 5'b?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSTR_XORI = { 17'b?, 3'b100, 5'b?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSTR_ORI = { 17'b?, 3'b110, 5'b?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSTR_ANDI = { 17'b?, 3'b111, 5'b?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSTR_SLLI = { 7'b0000000, 10'b?, 3'b001, 5'b?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSTR_SRLI = { 7'b0000000, 10'b?, 3'b101, 5'b?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSTR_SRAI = { 7'b0100000, 10'b?, 3'b101, 5'b?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSN_ADDI = { 17'b?, 3'b000, 5'b?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSN_SLTI = { 17'b?, 3'b010, 5'b?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSN_SLTIU = { 17'b?, 3'b011, 5'b?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSN_XORI = { 17'b?, 3'b100, 5'b?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSN_ORI = { 17'b?, 3'b110, 5'b?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSN_ANDI = { 17'b?, 3'b111, 5'b?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSN_SLLI = { 7'b0000000, 10'b?, 3'b001, 5'b?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSN_SRLI = { 7'b0000000, 10'b?, 3'b101, 5'b?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSN_SRAI = { 7'b0100000, 10'b?, 3'b101, 5'b?, {OPCODE_OP_IMM} };
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// OP
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parameter logic [31:0] INSTR_ADD = { 7'b0000000, 10'b?, 3'b000, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_SUB = { 7'b0100000, 10'b?, 3'b000, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_SLL = { 7'b0000000, 10'b?, 3'b001, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_SLT = { 7'b0000000, 10'b?, 3'b010, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_SLTU = { 7'b0000000, 10'b?, 3'b011, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_XOR = { 7'b0000000, 10'b?, 3'b100, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_SRL = { 7'b0000000, 10'b?, 3'b101, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_SRA = { 7'b0100000, 10'b?, 3'b101, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_OR = { 7'b0000000, 10'b?, 3'b110, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_AND = { 7'b0000000, 10'b?, 3'b111, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSN_ADD = { 7'b0000000, 10'b?, 3'b000, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSN_SUB = { 7'b0100000, 10'b?, 3'b000, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSN_SLL = { 7'b0000000, 10'b?, 3'b001, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSN_SLT = { 7'b0000000, 10'b?, 3'b010, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSN_SLTU = { 7'b0000000, 10'b?, 3'b011, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSN_XOR = { 7'b0000000, 10'b?, 3'b100, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSN_SRL = { 7'b0000000, 10'b?, 3'b101, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSN_SRA = { 7'b0100000, 10'b?, 3'b101, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSN_OR = { 7'b0000000, 10'b?, 3'b110, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSN_AND = { 7'b0000000, 10'b?, 3'b111, 5'b?, {OPCODE_OP} };
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// SYSTEM
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parameter logic [31:0] INSTR_CSRRW = { 17'b?, 3'b001, 5'b?, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSTR_CSRRS = { 17'b?, 3'b010, 5'b?, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSTR_CSRRC = { 17'b?, 3'b011, 5'b?, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSTR_CSRRWI = { 17'b?, 3'b101, 5'b?, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSTR_CSRRSI = { 17'b?, 3'b110, 5'b?, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSTR_CSRRCI = { 17'b?, 3'b111, 5'b?, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSTR_ECALL = { 12'b000000000000, 13'b0, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSTR_EBREAK = { 12'b000000000001, 13'b0, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSTR_MRET = { 12'b001100000010, 13'b0, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSTR_DRET = { 12'b011110110010, 13'b0, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSTR_WFI = { 12'b000100000101, 13'b0, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSN_CSRRW = { 17'b?, 3'b001, 5'b?, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSN_CSRRS = { 17'b?, 3'b010, 5'b?, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSN_CSRRC = { 17'b?, 3'b011, 5'b?, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSN_CSRRWI = { 17'b?, 3'b101, 5'b?, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSN_CSRRSI = { 17'b?, 3'b110, 5'b?, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSN_CSRRCI = { 17'b?, 3'b111, 5'b?, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSN_ECALL = { 12'b000000000000, 13'b0, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSN_EBREAK = { 12'b000000000001, 13'b0, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSN_MRET = { 12'b001100000010, 13'b0, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSN_DRET = { 12'b011110110010, 13'b0, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSN_WFI = { 12'b000100000101, 13'b0, {OPCODE_SYSTEM} };
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// RV32M
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parameter logic [31:0] INSTR_DIV = { 7'b0000001, 10'b?, 3'b100, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_DIVU = { 7'b0000001, 10'b?, 3'b101, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_REM = { 7'b0000001, 10'b?, 3'b110, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_REMU = { 7'b0000001, 10'b?, 3'b111, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_PMUL = { 7'b0000001, 10'b?, 3'b000, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_PMUH = { 7'b0000001, 10'b?, 3'b001, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_PMULHSU = { 7'b0000001, 10'b?, 3'b010, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_PMULHU = { 7'b0000001, 10'b?, 3'b011, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSN_DIV = { 7'b0000001, 10'b?, 3'b100, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSN_DIVU = { 7'b0000001, 10'b?, 3'b101, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSN_REM = { 7'b0000001, 10'b?, 3'b110, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSN_REMU = { 7'b0000001, 10'b?, 3'b111, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSN_PMUL = { 7'b0000001, 10'b?, 3'b000, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSN_PMUH = { 7'b0000001, 10'b?, 3'b001, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSN_PMULHSU = { 7'b0000001, 10'b?, 3'b010, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSN_PMULHU = { 7'b0000001, 10'b?, 3'b011, 5'b?, {OPCODE_OP} };
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// LOAD & STORE
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parameter logic [31:0] INSTR_LOAD = {25'b?, {OPCODE_LOAD } };
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parameter logic [31:0] INSTR_STORE = {25'b?, {OPCODE_STORE} };
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parameter logic [31:0] INSN_LOAD = {25'b?, {OPCODE_LOAD } };
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parameter logic [31:0] INSN_STORE = {25'b?, {OPCODE_STORE} };
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// MISC-MEM
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parameter logic [31:0] INSTR_FENCE = { 17'b?, 3'b000, 5'b?, {OPCODE_MISC_MEM} };
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parameter logic [31:0] INSN_FENCE = { 17'b?, 3'b000, 5'b?, {OPCODE_MISC_MEM} };
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parameter logic [31:0] INSN_FENCEI = { 17'b0, 3'b001, 5'b0, {OPCODE_MISC_MEM} };
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// Compressed Instructions
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// C0
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parameter logic [15:0] INSTR_CADDI4SPN = { 3'b000, 11'b?, {OPCODE_C0} };
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parameter logic [15:0] INSTR_CLW = { 3'b010, 11'b?, {OPCODE_C0} };
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parameter logic [15:0] INSTR_CSW = { 3'b110, 11'b?, {OPCODE_C0} };
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parameter logic [15:0] INSN_CADDI4SPN = { 3'b000, 11'b?, {OPCODE_C0} };
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parameter logic [15:0] INSN_CLW = { 3'b010, 11'b?, {OPCODE_C0} };
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parameter logic [15:0] INSN_CSW = { 3'b110, 11'b?, {OPCODE_C0} };
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// C1
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parameter logic [15:0] INSTR_CADDI = { 3'b000, 11'b?, {OPCODE_C1} };
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parameter logic [15:0] INSTR_CJAL = { 3'b001, 11'b?, {OPCODE_C1} };
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parameter logic [15:0] INSTR_CJ = { 3'b101, 11'b?, {OPCODE_C1} };
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parameter logic [15:0] INSTR_CLI = { 3'b010, 11'b?, {OPCODE_C1} };
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parameter logic [15:0] INSTR_CLUI = { 3'b011, 11'b?, {OPCODE_C1} };
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parameter logic [15:0] INSTR_CBEQZ = { 3'b110, 11'b?, {OPCODE_C1} };
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parameter logic [15:0] INSTR_CBNEZ = { 3'b111, 11'b?, {OPCODE_C1} };
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parameter logic [15:0] INSTR_CSRLI = { 3'b100, 1'b?, 2'b00, 8'b?, {OPCODE_C1} };
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parameter logic [15:0] INSTR_CSRAI = { 3'b100, 1'b?, 2'b01, 8'b?, {OPCODE_C1} };
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parameter logic [15:0] INSTR_CANDI = { 3'b100, 1'b?, 2'b10, 8'b?, {OPCODE_C1} };
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parameter logic [15:0] INSTR_CSUB = { 3'b100, 1'b0, 2'b11, 3'b?, 2'b00, 3'b?, {OPCODE_C1} };
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parameter logic [15:0] INSTR_CXOR = { 3'b100, 1'b0, 2'b11, 3'b?, 2'b01, 3'b?, {OPCODE_C1} };
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parameter logic [15:0] INSTR_COR = { 3'b100, 1'b0, 2'b11, 3'b?, 2'b10, 3'b?, {OPCODE_C1} };
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parameter logic [15:0] INSTR_CAND = { 3'b100, 1'b0, 2'b11, 3'b?, 2'b11, 3'b?, {OPCODE_C1} };
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parameter logic [15:0] INSN_CADDI = { 3'b000, 11'b?, {OPCODE_C1} };
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parameter logic [15:0] INSN_CJAL = { 3'b001, 11'b?, {OPCODE_C1} };
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parameter logic [15:0] INSN_CJ = { 3'b101, 11'b?, {OPCODE_C1} };
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parameter logic [15:0] INSN_CLI = { 3'b010, 11'b?, {OPCODE_C1} };
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parameter logic [15:0] INSN_CLUI = { 3'b011, 11'b?, {OPCODE_C1} };
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parameter logic [15:0] INSN_CBEQZ = { 3'b110, 11'b?, {OPCODE_C1} };
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parameter logic [15:0] INSN_CBNEZ = { 3'b111, 11'b?, {OPCODE_C1} };
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parameter logic [15:0] INSN_CSRLI = { 3'b100, 1'b?, 2'b00, 8'b?, {OPCODE_C1} };
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parameter logic [15:0] INSN_CSRAI = { 3'b100, 1'b?, 2'b01, 8'b?, {OPCODE_C1} };
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parameter logic [15:0] INSN_CANDI = { 3'b100, 1'b?, 2'b10, 8'b?, {OPCODE_C1} };
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parameter logic [15:0] INSN_CSUB = { 3'b100, 1'b0, 2'b11, 3'b?, 2'b00, 3'b?, {OPCODE_C1} };
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parameter logic [15:0] INSN_CXOR = { 3'b100, 1'b0, 2'b11, 3'b?, 2'b01, 3'b?, {OPCODE_C1} };
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parameter logic [15:0] INSN_COR = { 3'b100, 1'b0, 2'b11, 3'b?, 2'b10, 3'b?, {OPCODE_C1} };
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parameter logic [15:0] INSN_CAND = { 3'b100, 1'b0, 2'b11, 3'b?, 2'b11, 3'b?, {OPCODE_C1} };
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// C2
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parameter logic [15:0] INSTR_CSLLI = { 3'b000, 11'b?, {OPCODE_C2} };
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parameter logic [15:0] INSTR_CLWSP = { 3'b010, 11'b?, {OPCODE_C2} };
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parameter logic [15:0] INSTR_SWSP = { 3'b110, 11'b?, {OPCODE_C2} };
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parameter logic [15:0] INSTR_CMV = { 3'b100, 1'b0, 10'b?, {OPCODE_C2} };
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parameter logic [15:0] INSTR_CADD = { 3'b100, 1'b1, 10'b?, {OPCODE_C2} };
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parameter logic [15:0] INSTR_CEBREAK = { 3'b100, 1'b1, 5'b0, 5'b0, {OPCODE_C2} };
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parameter logic [15:0] INSTR_CJR = { 3'b100, 1'b0, 5'b?, 5'b0, {OPCODE_C2} };
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parameter logic [15:0] INSTR_CJALR = { 3'b100, 1'b1, 5'b?, 5'b0, {OPCODE_C2} };
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parameter logic [15:0] INSN_CSLLI = { 3'b000, 11'b?, {OPCODE_C2} };
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parameter logic [15:0] INSN_CLWSP = { 3'b010, 11'b?, {OPCODE_C2} };
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parameter logic [15:0] INSN_SWSP = { 3'b110, 11'b?, {OPCODE_C2} };
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parameter logic [15:0] INSN_CMV = { 3'b100, 1'b0, 10'b?, {OPCODE_C2} };
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parameter logic [15:0] INSN_CADD = { 3'b100, 1'b1, 10'b?, {OPCODE_C2} };
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parameter logic [15:0] INSN_CEBREAK = { 3'b100, 1'b1, 5'b0, 5'b0, {OPCODE_C2} };
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parameter logic [15:0] INSN_CJR = { 3'b100, 1'b0, 5'b?, 5'b0, {OPCODE_C2} };
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parameter logic [15:0] INSN_CJALR = { 3'b100, 1'b1, 5'b?, 5'b0, {OPCODE_C2} };
|
||||
|
||||
endpackage
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|
|
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Loading…
Add table
Add a link
Reference in a new issue